參數(shù)資料
型號： ISP1581
廠商： NXP Semiconductors N.V.
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： 通用串行總線2.0高速接口設(shè)備
文件頁數(shù)： 35/73頁
文件大?。?/td> 1819K
代理商： ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
35 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
9.4.7
DMA Interrupt Reason register (address: 50H)
This 2-byte register shows the source(s) of a DMA interrupt. Each bit is refreshed
after a DMA command has been executed. An interrupt source is cleared by writing a
logic 1 to the corresponding bit. The bit allocation is given in
Table 53
.
Table 52: Task File register 3F7 (address: 4FH): bit allocation
CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = H.
Bit
7
Symbol
Reset
Bus reset
Access
6
5
4
3
2
1
0
drive address (ATA) or reserved (ATAPI)
00H
00H
R/W
Table 53: DMA Interrupt Reason register: bit allocation
Bit
15
Symbol
reserved
14
13
12
11
10
9
8
reserved
reserved
reserved
reserved
reserved
INTRQ_
PENDING
0
0
R/W
1
CMD_
INTRQ_OK
0
0
R/W
DMA_
XFER_OK
0
0
R/W
0
reserved
Reset
Bus reset
Access
Bit
Symbol
0
0
0
0
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
BSY_
DONE
0
0
R/W
R/W
2
TF_RD_
DONE
0
0
R/W
1F0_WF_E
1F0_WF_F
1F0_RF_E
READ_1F0
Reset
Bus reset
Access
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 54: DMA Interrupt Reason Register: bit description
Bit
Symbol
15 to 10 -
9
INTRQ_PENDING
Description
reserved
A logic 1 indicates that a pending interrupt was detected on
pin INTRQ.
A logic 1 indicates that the DMA transfer has been completed
(DMA Transfer Counter has become zero). This bit is only
used in GDMA (slave) mode and MDMA (master) mode.
A logic 1 indicates that the 1F0 write FIFO is empty and the
microcontroller can start writing data.
A logic 1 indicates that the 1F0 write FIFO is full and the
microcontroller must stop writing data.
A logic 1 indicates that 1F0 read FIFO is empty and the
microcontroller must stop reading data.
A logic 1 indicates that 1F0 FIFO contains unread data and
the microcontroller can start reading data.
A logic 1 indicates that the BSY status bit has become zero
and polling has been stopped.
8
DMA_XFER_OK
7
1F0_WF_E
6
1F0_WF_F
5
1F0_RF_E
4
READ_1F0
3
BSY_DONE
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