參數(shù)資料
型號(hào)： ISP1581
廠商： NXP Semiconductors N.V.
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： 通用串行總線2.0高速接口設(shè)備
文件頁(yè)數(shù)： 20/73頁(yè)
文件大?。?/td> 1819K
代理商： ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
20 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
Host to device (OUT endpoint)
: After each read action an internal counter is
auto-decremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next
location in the RX FIFO. When all bytes have been read, the buffer contents can be
cleared via the Control Function register (bit CLBUF). A new data packet can then be
received on the next OUT token.
Remark:
The buffer can be validated or cleared automatically by using the Buffer
Length register (see
Table 21
).
9.3.4
Buffer Length register (address: 1CH)
This 2-byte register determines the current packet size (DATACOUNT) of the indexed
endpoint FIFO. The bit allocation is given in
Table 21
.
The Buffer Length register is automatically loaded with the FIFO size, when the
Endpoint MaxPacketSize register is written (see
Table 22
). A smaller value can be
written when required. After a bus reset the Buffer Length register is made zero.
IN endpoint:
When writing bytes into the TX FIFO, the buffer is automatically
validated when DATACOUNT exceeds MaxPacketSize. During the subsequent packet
transmission DATACOUNT is decremented with the number of bytes sent. This
process is repeated until the number of remaining bytes is less than MaxPacketSize
(case I) or zero (case II). In case I, the remaining bytes are automatically validated
and a short packet is sent. In case II, a final empty packet will be appended if bit
NOEMPKT in the Endpoint Type register is cleared (see
Table 24
). Otherwise (if bit
NOEMPKT is set), data transfer is considered finished when the buffer is empty.
OUT endpoint:
The DATACOUNT value is automatically initialized to the number of
data bytes sent by the host on each ACK. After reading DATACOUNT bytes from the
RX buffer, the buffer is automatically cleared to allow the next packet to be received
from the host.
Remark:
For a 16-bit bus, the last byte of an odd-sized packet is output as the lower
byte (LSB).
Table 19: Data Port register: bit allocation
Bit
15
Symbol
Reset
Bus reset
Access
Bit
7
Symbol
Reset
Bus reset
Access
14
13
12
DATAPORT[15:8]
00H
00H
R/W
4
DATAPORT[7:0]
00H
00H
R/W
11
10
9
8
6
5
3
2
1
0
Table 20: Data Port register: bit description
Bit
Symbol
15 to 8
DATAPORT[15:8]
7 to 0
DATAPORT[7:0]
Description
data (upper byte); not used in 8-bit bus mode
data (lower byte)
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