參數(shù)資料
型號(hào)： ISP1581
廠商： NXP Semiconductors N.V.
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： 通用串行總線2.0高速接口設(shè)備
文件頁(yè)數(shù)： 23/73頁(yè)
文件大?。?/td> 1819K
代理商： ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
23 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
Table 26: Short Packet register: bit allocation
Bit
15
Symbol
OUT7SH
Reset
0
Bus reset
0
Access
R
Bit
7
Symbol
reserved
Reset
0
Bus reset
0
Access
R/W
14
13
12
11
10
9
8
OUT6SH
0
0
R
6
reserved
0
0
R/W
OUT5SH
0
0
R
5
reserved
0
0
R/W
OUT4SH
0
0
R
4
reserved
0
0
R/W
OUT3SH
0
0
R
3
reserved
0
0
R/W
OUT2SH
0
0
R
2
reserved
0
0
R/W
OUT1SH
0
0
R
1
reserved
0
0
R/W
OUT0SH
0
0
R
0
reserved
0
0
R/W
Table 27: Short Packet register: bit description
Bit
Symbol
15
OUT7SH
Description
A logic 1 indicates that a Short Packet was received on
OUTendpoint 7. A logic 0 indicates that the buffer is full.
A logic 1 indicates that a Short Packet was received on
OUTendpoint 6. A logic 0 indicates that the buffer is full.
A logic 1 indicates that a Short Packet was received on
OUTendpoint 5. A logic 0 indicates that the buffer is full.
A logic 1 indicates that a Short Packet was received on
OUTendpoint 4. A logic 0 indicates that the buffer is full.
A logic 1 indicates that a Short Packet was received on
OUTendpoint 3. A logic 0 indicates that the buffer is full.
A logic 1 indicates that a Short Packet was received on
OUTendpoint 2. A logic 0 indicates that the buffer is full.
A logic 1 indicates that a Short Packet was received on
OUTendpoint 1. A logic 0 indicates that the buffer is full.
A logic 1 indicates that a Short Packet was received on
OUTendpoint 0. A logic 0 indicates that the buffer is full.
reserved
14
OUT6SH
13
OUT5SH
12
OUT4SH
11
OUT3SH
10
OUT2SH
9
OUT1SH
8
OUT0SH
7 to 0
-
相關(guān)PDF資料
PDF描述
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
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