參數(shù)資料
型號: ISP1581
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus 2.0 high-speed interface device
中文描述: 通用串行總線2.0高速接口設(shè)備
文件頁數(shù): 30/73頁
文件大?。?/td> 1819K
代理商: ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
30 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
[1]
[2]
DREQ is asserted only if space (writing) or data (reading) is available in the FIFO.
This process is stopped when the transfer FIFO becomes empty.
9.4.4
DMA Hardware register (address: 3CH)
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
Table 37
.
This register determines the polarity of the bus control signals (EOT, DACK, DREQ,
DIOR, DIOW) and the DMA mode (master or slave). It also controls whether the
upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]), for modes
GDMA (slave) and MDMA (master) only.
6 to 4
BURST[2:0]
These bits select the DMA burst length and the DREQ timing
(GDMA Slave mode only):
00H —
DREQ is asserted until the last byte/word is
transferred or until the FIFO becomes full or empty
01H —
DREQ is asserted and negated for each byte/word
transferred
[1][2]
02H —
DREQ is asserted and negated for every
2 bytes/words transferred
[1][2]
03H —
DREQ is asserted and negated for every
4 bytes/words transferred
[1][2]
04H —
DREQ is asserted and negated for every
8 bytes/words transferred
[1][2]
05H —
DREQ is asserted and negated for every
12 bytes/words transferred
[1][2]
06H —
DREQ is asserted and negated for every
16 bytes/words transferred
[1][2]
07H —
DREQ is asserted and negated for every
32 bytes/words transferred
[1][2]
.
These bits only affect the GDMA (slave) and MDMA (master)
handshake signals:
00H —
DIOR (master) or DIOW (slave): strobes data from the
DMA bus into the ISP1581; DIOW (master) or DIOR (slave):
puts data from the ISP1581 on the DMA bus
01H —
DIOR (master) or DACK (slave) strobes the data from
the DMA bus into the ISP1581; DACK (master) or DIOR
(slave) puts the data from the ISP1581 on the DMA bus
02H —
DACK (master and slave) strobes the data from the
DMA bus into the ISP1581 and also puts the data from the
ISP1581 on the DMA bus
03H —
reserved.
reserved
This bit selects the DMA bus width for GDMA (slave) and
MDMA (master):
0 —
8-bit data bus
1 —
16-bit data bus.
3 to 2
MODE[1:0]
1
0
-
WIDTH
Table 36: DMA Configuration register: bit description
…continued
Bit
Symbol
Description
相關(guān)PDF資料
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