參數(shù)資料
型號: ISP1581
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus 2.0 high-speed interface device
中文描述: 通用串行總線2.0高速接口設(shè)備
文件頁數(shù): 32/73頁
文件大小: 1819K
代理商: ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
32 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
[1]
The cycle duration for UDMA mode 3 is the same as for UDMA mode 2 (see
Table 87
).
9.4.6
Task File registers (addresses: 40H to 4FH)
These registers allow direct access to the internal registers of an ATAPI peripheral
using PIO mode. The supported Task File registers and their functions are shown in
Table 41
. The correct peripheral register is automatically addressed via pins CS1,
CS0, DA2, DA1 and DA0 (see
Table 42
).
Table 39: DMA Strobe Timing register: bit allocation
Bit
7
Symbol
reserved
Reset
0
Bus reset
0
Access
R/W
6
5
4
3
2
1
0
reserved
0
0
R/W
reserved
0
0
R/W
DMA_STROBE_CNT[4:0]
1FH
1FH
R/W
Table 40: DMA Strobe Timing register: bit description
Bit
Symbol
7 to 5
-
4 to 0
DMA_
STROBE_
CNT[4:0]
Description
reserved.
These bits select the strobe duration for UDMA_MODE = 03H
(see
Table 35
). The strobe duration is (N+1) cycles
[1]
, with N
representing the value of DMA_.STROBE_CNT.
Table 41: Task File register functions
Address (Hex)
ATA function
1F0
data (16-bits)
1F1
error/feature
1F2
sector count
1F3
sector number/LBA[7:0]
1F4
cylinder low/LBA[15:8]
1F5
cylinder high/LBA[23:16]
1F6
drive/head/LBA[27:24]
1F7
command
3F6
alternate status/command
3F7
drive address
ATAPI function
data (16-bits)
error/feature
interrupt reason
reserved
cylinder low
cylinder high
drive select
status/command
alternate status/command
reserved
Table 42: ATAPI peripheral register addressing
Task file
CS1
1F0
H
1F1
H
1F2
H
1F3
H
1F4
H
1F5
H
1F6
H
CS0
L
L
L
L
L
L
L
DA2
L
L
L
L
H
H
H
DA1
L
L
H
H
L
L
H
DA0
L
H
L
H
L
H
L
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