參數(shù)資料
型號(hào): ISP1581
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus 2.0 high-speed interface device
中文描述: 通用串行總線2.0高速接口設(shè)備
文件頁數(shù): 21/73頁
文件大?。?/td> 1819K
代理商: ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
21 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
9.3.5
Endpoint MaxPacketSize register (address: 04H)
This register determines the maximum packet size for all endpoints except Control 0.
The register contains 2 bytes and the bit allocation is given in
Table 22
.
Each time the register is written, the Buffer Length registers of all endpoints are
re-initialized to the FFOSZ field value. The NTRANS bits control the number of
transactions allowed in a single micro-frame (for high-speed operation only).
Table 21: Buffer Length register: bit allocation
Bit
15
Symbol
Reset
Bus reset
Access
Bit
7
Symbol
Reset
Bus reset
Access
14
13
12
11
10
9
8
DATACOUNT[15:8]
00H
00H
R/W
4
DATACOUNT[7:0]
00H
00H
R/W
6
5
3
2
1
0
Table 22: Endpoint MaxPacketSize register: bit allocation
Bit
15
Symbol
reserved
reserved
Reset
0
Bus reset
0
Access
R/W
Bit
7
Symbol
Reset
Bus reset
Access
14
13
12
11
10
9
8
reserved
0
0
R/W
5
NTRANS[1:0]
00H
00H
R/W
4
FFOSZ[7:0]
00H
00H
R/W
FFOSZ[10:8]
00H
00H
R/W
1
0
0
R/W
6
3
2
0
Table 23: Endpoint MaxPacketSize register: bit description
Bit
Symbol
Description
15 to 13
reserved
reserved
12 to 11
NTRANS[1:0]
Number of Transactions
(HS mode only):
0 —
1 packet per microframe
1 —
2 packets per microframe
2 —
3 packets per microframe
3 —
reserved.
10 to 0
FFOSZ[10:0]
FIFO Size
: Sets the FIFO size in bytes for the indexed endpoint.
Applies to both HS and FS operation.
Remark:
A FIFO size of zero will disable the endpoint.
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