參數(shù)資料
型號: ISP1581
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus 2.0 high-speed interface device
中文描述: 通用串行總線2.0高速接口設(shè)備
文件頁數(shù): 12/73頁
文件大?。?/td> 1819K
代理商: ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
12 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
DMA registers
DMA Command
DMA Transfer Counter
DMA Configuration
DMA controller
DMA controller
DMA controller
30
34
38 (byte 0)
controls all DMA transfers
sets byte count for DMA Transfer
sets GDMA configuration (counter enable,
burst length, data strobing, bus width)
sets ATA configuration (IORDY enable,
mode selection: ATA/UDMA/MDMA/PIO)
endian type, master/slave selection, signal
polarity for DACK, DREQ, DIOW, DIOR
single address word register: byte 0 (lower
byte) is accessed first
IDE device access
IDE device access
IDE device access
IDE device access
IDE device access
IDE device access
IDE device access (write only; reading
returns 00H)
IDE device access
IDE device access
shows reason (source) for DMA interrupt
1
4
1
39 (byte 1)
1
DMA Hardware
DMA controller
3C
1
1F0 Task File
ATAPI peripheral
40
2
1F1Task File
1F2 Task File
1F3 Task File
1F4 Task File
1F5 Task File
1F6 Task File
1F7 Task File
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
48
49
4A
4B
4C
4D
44
1
1
1
1
1
1
1
3F6 Task File
3F7 Task File
DMA Interrupt Reason
ATAPI peripheral
ATAPI peripheral
DMA controller
4E
4F
50 (byte 0)
51 (byte 1)
54 (byte 0)
55 (byte 1)
58
60
1
1
1
1
1
1
1
1
DMA Interrupt Enable
DMA controller
enables DMA interrupt sources
DMA Endpoint
DMA Strobe Timing
General registers
Interrupt
Chip ID
Frame Number
DMA controller
DMA controller
selects endpoint FIFO, data flow direction
strobe duration in UDMA/MDMA mode
device
device
device
18
70
74
shows interrupt sources
product ID code and hardware version
last successfully received Start Of Frame:
lower byte (byte 0) is accessed first
allows save/restore of firmware status
during ‘suspend’
re-enables register access after ‘suspend’
direct setting of D
+
, D
states, loopback
mode, internal transceiver test (PHY)
4
3
2
Scratch
device
78
2
Unlock Device
Test Mode
device
PHY
7C
84
2
1
Table 4:
Name
Register summary
…continued
Destination
Address
(Hex)
Description
Size
(bytes)
相關(guān)PDF資料
PDF描述
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
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