參數資料
型號: ISP1581
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus 2.0 high-speed interface device
中文描述: 通用串行總線2.0高速接口設備
文件頁數: 31/73頁
文件大小: 1819K
代理商: ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
31 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
[1]
Nibble = 4 bits. MSN: Most Significant Nibble, LSN: Least Significant Nibble.
9.4.5
DMA Strobe Timing register (address: 60H)
This 1-byte register controls the strobe timings for UDMA and MDMA mode, when the
UDMA_MODE bits in the DMA Configuration register have been set to 03H. The bit
allocation is given in
Table 39
.
Table 37: DMA Hardware register: bit allocation (modes GDMA, MDMA (Master) and MDMA (ATA) only)
Bit
7
6
5
Symbol
ENDIAN[1:0]
EOT_
POL
Reset
00H
0
Bus reset
00H
0
Access
R/W
R/W
4
3
2
1
0
MASTER
ACK_
POL
0
0
R/W
DREQ_
POL
1
1
R/W
WRITE_
POL
0
0
R/W
READ_
POL
0
0
R/W
0
0
R/W
Table 38: DMA Hardware register: bit description
Bit
Symbol
7 to 6
ENDIAN[1:0]
Description
These bits determine whether the data bus is swapped between
internal RAM and the DMA bus: nibbles
[1]
(8-bit bus) or bytes
(16-bit bus). This only applies for modes GDMA (slave) and
MDMA (master).
00H —
normal data representation
8-bit bus: MSN on DATA[7:4], LSN on DATA[3:0];
16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0]
01H —
swapped data representation
8-bit bus: MSN on DATA[3:0], LSN on DATA[7:4];
16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8]
02H, 03H —
reserved.
Selects the polarity of the End Of Transfer input (used in GDMA
slave mode only):
0 —
EOT is active LOW
1 —
EOT is active HIGH.
Selects the DMA master/slave mode:
0 —
GDMA slave mode.
1 —
MDMA master mode.
Selects the DMA acknowledgement polarity:
0 —
DACK is active LOW
1 —
DACK is active HIGH.
Selects the DMA request polarity:
0 —
DREQ is active LOW
1 —
DREQ is active HIGH.
Selects the DIOW strobe polarity.
0 —
DIOW is active LOW
1 —
DIOW is active HIGH.
Selects the DIOR strobe polarity.
0 —
DIOR is active LOW
1 —
DIOR is active HIGH.
5
EOT_POL
4
MASTER
3
ACK_POL
2
DREQ_POL
1
WRITE_POL
0
READ_POL
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