參數資料
型號： ISP1581
廠商： NXP Semiconductors N.V.
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： 通用串行總線2.0高速接口設備
文件頁數： 14/73頁
文件大小： 1819K
代理商： ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
14 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
9.2.2
Mode register (address: 0CH)
This register consists of 1 byte (bit allocation: see
Table 7
). In 16-bit bus mode the
upper byte is ignored.
The Mode register controls the resume, suspend and wake-up behaviour, interrupt
activity, soft reset, clock signals and SoftConnect operation. This register also
controls the Power Off mode during ‘suspend’ state.
Table 7:
Bit
Symbol
Reset
Bus reset
Access
Mode register: bit allocation
7
CLKAON
0
0
R/W
6
5
4
3
2
1
0
SNDRSU
0
0
R/W
GOSUSP
0
0
R/W
SFRESET
0
0
R/W
GLINTENA
0
unchanged
R/W
WKUPCS
0
0
R/W
PWROFF
0
unchanged
R/W
SOFTCT
0
unchanged
R/W
Table 8:
Bit
7
Mode register: bit description
Symbol
CLKAON
Description
Clock Always On:
A logic 1 indicates that the internal clocks
are always running even during ‘suspend’ state. A logic 0
switches off the internal oscillator and PLL, when they are not
needed. During ‘suspend’ state, this bit must be set to logic 0 to
meet the suspend current requirements. The clock is stopped
after a delay of approximately 2 ms, following the setting of bit
GOSUSP.
Send Resume:
Writing a logic 1 followed by a logic 0 will
generate an upstream ‘resume’ signal of 10 ms duration, after a
5 ms delay.
Go Suspend:
Writing a logic 1 followed by a logic 0 will activate
‘suspend’ mode.
Soft Reset:
Writing a logic 1 followed by a logic 0 will enable a
software-initiated reset to ISP1581. A soft reset is similar to a
hardware-initiated reset (via the RESET pin).
Global Interrupt Enable:
A logic 1 enables all interrupts.
Individual interrupts can be masked OFF by clearing the
corresponding bits in the Interrupt Enable register. Bus reset
value: unchanged.
Wake-up on Chip Select:
A logic 1 enables remote wake-up
via a LOW level on input CS.
Power Off mode:
A logic 1 enables powering-off during
‘suspend’ state. Output SUSPEND is configured as a power
switch control signal for external devices (HIGH during
‘suspend’). Bus reset value: unchanged.
SoftConnect:
A logic 1 enables the connection of the 1.5 k
pull-up resistor on pin RPU to the D
+
line. Bus reset value:
unchanged.
6
SNDRSU
5
GOSUSP
4
SFRESET
3
GLINTENA
2
WKUPCS
1
PWROFF
0
SOFTCT
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