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參數(shù)資料
| 型號： | HB52E169E12 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 128 MB Registered SDRAM DIMM(128 MB 寄存同步DRAM DIMM) |
| 中文描述： | 128 MB的注冊SDRAM的內(nèi)存（128 MB的寄存同步的DRAM內(nèi)存） |
| 文件頁數(shù)： | 17/53頁 |
| 文件大小： | 1737K |
| 代理商： | HB52E169E12 |
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HB52E169E12-F
17
Row address strobe and bank activate [ACTV]:
This command activates the bank that is selected by Bank
select address (BA) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0
is activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High,
bank 2 is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]:
This command starts precharge operation for the bank selected by Bank
select address (BA). If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is
selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]:
This command starts a precharge operation for all banks.
Refresh [REF/SELF]:
This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]:
The SDRAM module has a mode register that defines how it operates. The mode
register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the
mode register configuration. After power on, the contents of the mode register are undefined, execute the
mode register set command to set up the mode register.
DQMB Truth Table
Note: H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
Write: I
DID
is needed.
Read: I
DOD
is needed.
The SDRAM module can mask input/output data by means of DQMB.
During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the
other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is
held (the new data is not written). Desired data can be masked during burst read or burst write by setting
DQMB. For details, refer to the DQMB control section of the SDRAM module operating instructions.
CKE Truth Table
Command
Write enable/output enable
Write inhibit/output disable
Symbol
ENB
MASK
CKE
n - 1
H
H
DQMB
L
H
n
×
×
Current state
Active
Any
Clock suspend
Idle
Idle
Idle
Command
Clock suspend mode entry
Clock suspend
Clock suspend mode exit
Auto-refresh command (REF)
Self-refresh entry (SELF)
Power down entry
CKE
n - 1
H
L
L
H
H
H
H
S
H
×
×
L
L
L
H
RE
×
×
×
L
L
H
×
CE
×
×
×
L
L
H
×
W
×
×
×
H
H
H
×
Address
×
×
×
×
×
×
×
n
L
L
H
H
L
L
L
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HB52E648EN | 512 MB Unbuffered SDRAM DIMM(512 MB 未緩沖同步DRAM DIMM) |
| HB52E649EN | 512 MB Unbuffered SDRAM DIMM(512 MB 未緩沖同步DRAM DIMM) |
| HB52E649E12 | THERMISTOR, NTC; Series:B575; Thermistor type:NTC; Resistance:10kR; Tolerance, resistance:+/-1%; Beta value:3450; Temperature, lower limit, beta value:0(degree C); Temperature, upper limit, beta value:100(degree C); Temp, op. RoHS Compliant: Yes |
| HB52E649E12-A6B | 512 MB Registered SDRAM DIMM 64-Mword 】 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M 】 4 Components) PC100 SDRAM |
| HB52E649E12-B6B | 512 MB Registered SDRAM DIMM 64-Mword 】 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M 】 4 Components) PC100 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HB52E169E1-B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HB52E169EN-B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HB52E328EM-A6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM DIMM |
| HB52E328EM-B6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM DIMM |
| HB52E329EM-A6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM DIMM |
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