參數(shù)資料
型號(hào): HB52E169E12
廠商: Hitachi,Ltd.
英文描述: 128 MB Registered SDRAM DIMM(128 MB 寄存同步DRAM DIMM)
中文描述: 128 MB的注冊(cè)SDRAM的內(nèi)存(128 MB的寄存同步的DRAM內(nèi)存)
文件頁(yè)數(shù): 14/53頁(yè)
文件大小: 1737K
代理商: HB52E169E12
HB52E169E12-F
14
5. t
CES
defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
Input and output timing reference levels: 1.5 V
Input waveform and output load: See following figures
Relationship Between Frequency and Minimum Latency
Parameter
Frequency (MHz)
t
CK
(ns)
Active command to column command (same bank)
Active command to active command (same bank)
HITACHI
Symbol
I
RCD
I
RC
PC100
Symbol
HB52E169E12
-A6F/B6F
100
10
2
7
Notes
1
= [I
RAS
+ I
RP
]
1
1
1
1
Active command to precharge command (same bank) I
RAS
Precharge command to active command (same bank) I
RP
Write recovery or data-in to precharge command
(same bank)
Active command to active command (different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input
5
2
1
I
DPL
Tdpl
I
RRD
I
SREX
I
APW
2
2
3
1
2
= [I
DPL
+ I
RP
]
Tsrx
Tdal
I
SEC
7
= [I
RC
]
3
Precharge command to high impedance
(CE latency = 3)
(CE latency = 4)
Last data out to active command (auto precharge)
(same bank)
Last data out to precharge (early precharge)
(CE latency = 3)
(CE latency = 4)
Column command to column command
Write command to data in latency
DQMB to data in
DQMB to data out
CKE to CK disable
Register set to active command
I
HZP
I
HZP
I
APR
Troh
Troh
3
4
0
I
EP
I
EP
I
CCD
I
WCD
I
DID
I
DOD
I
CLE
I
RSA
–2
–3
1
1
1
3
2
1
Tccd
Tdwd
Tdqm
Tdqz
Tcke
Tmrd
t
T
2.4 V
0.4 V0.8 V
2.0 V
input
t
T
DQ
CL
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