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參數(shù)資料
| 型號： | H5MS5162DFR-K3M |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA60 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60 |
| 文件頁數(shù)： | 61/62頁 |
| 文件大?。?/td> | 1314K |
| 代理商： | H5MS5162DFR-K3M |
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Rev 1.3 / Apr. 2009
8
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
Mobile DDR SDRAM PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
CK, CK
INPUT
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossings of CK and CK (both directions of crossing).
CKE
INPUT
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in
any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is
achieved asynchronously.
CS
INPUT
Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command
code.
RAS, CAS, WE
INPUT
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered
BA0, BA1
INPUT
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied. BA0 and BA1 also determine which mode register
is to be loaded during a MODE REGISTER SET command (MRS, EMRS or SRR).
A0 ~ A12
INPUT
Address inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. The address inputs also provide the op-code during
a MODE REGISTER SET command. A10 sampled during a PRECHARGE command deter-
mines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1.
For 512Mb (x16), Row Address: A0 ~ A12, Column Address: A0 ~ A9
Auto-precharge flag: A10
DQ0 ~ DQ15
I/O
Data Bus: data input / output pin
LDM ~ UDM
INPUT
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled. HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ
and DQS loading.
For x16 devices, LDM corresponds to the data on DQ0-DQ7, and UDM corresponds to the
data on DQ8-DQ15.
LDQS ~ UDQS
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data,
center-aligned with write data. Used to capture write data.
For x16 device, LDQS corresponds to the data on DQ0-DQ7, and UDQS corresponds to the
data on DQ8-DQ15.
VDD
SUPPLY
Power supply
VSS
SUPPLY
Ground
VDDQ
SUPPLY
I/O Power supply
VSSQ
SUPPLY
I/O Ground
NC
-
No Connect: No internal electrical connection is present.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| H5MS5162DFR-L3M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM |
| H5MS5162EFR | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM) |
| H5MS5162EFR-J3M | 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes |
| H5MS5162FFR-E3M | 制造商:SK Hynix Inc 功能描述: |
| H5N1503P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching |
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