參數(shù)資料
型號(hào): H5MS5162DFR-K3M
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, 0.5 ns, PBGA60
封裝: 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60
文件頁數(shù): 53/62頁
文件大?。?/td> 1314K
代理商: H5MS5162DFR-K3M
Rev 1.3 / Apr. 2009
57
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
CAS LATENCY DEFINITION
CAS latency definition of Mobile DDR SDRAM must be must be loaded when all banks are idle, and the controller must
wait the specified time before initiating the subsequent operation.
CAS latency definition: with CL = 3 the first data element is valid at (2 * tCK + tAC) after the clock at which the READ
command was registered (See Figure 2)
CAS LATENCY DEFINITION
NOTE
1. DQ transitioning after DQS transition define tDQSQ window.
2. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
3. tAC is the DQ output window relative to CK, and is the long term component of DQ skew.
Read
NOP
T
0
T
1
T
3
T
4
T
5
T
2
T
2n
T
3n
T
4n
T
5n
T
6
NOP
T
2
T
2n
T
3
T
3n
T
4
T
4n
T
5
T
5n
All DQ values,
collectively
2
CL = 3
tLZ
tRPRE
tLZ
tDQSCK
tRPST
DQS
CMD
CK
tAC
tDQSQ
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