參數(shù)資料
型號： H5MS5162DFR-K3M
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 0.5 ns, PBGA60
封裝： 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60
文件頁數(shù)： 17/62頁
文件大?。?/td> 1314K
代理商： H5MS5162DFR-K3M
Rev 1.3 / Apr. 2009
24
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) (Sheet 1 of 2)
Parameter
Symbol
DDR400
DDR370 DDR333
DDR266
DDR200
Unit Note
Min Max Min Max Min Max Min Max Min Max
DQ Output Access Time (from CK, CK)
tAC
2.0
5.0
2.0
5.0
2.0
5.0
2.5
6.0
2.5
7.0
ns
DQS Output Access Time (from CK, CK) tDQSCK
2.0
5.0
2.0
5.0
2.0
5.0
2.5
6.0
2.5
7.0
ns
Clock High-level Width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock Low-level Width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock Half Period
tHP
tCL,
tCH
(Min)
-
tCL,
tCH
(Min)
-
tCL,
tCH
(Min)
-
tCL,
tCH
(Min)
-
tCL,
tCH
(Min)
-
ns
1,2
System
Clock
Cycle
Time
CL = 3
tCK3
5.0
-
5.4
-
6.0
-
7.5
-
10
-
ns
3
CL = 2
tCK2
12
-
12
-
12
-
12
-
15
-
ns
DQ and DM Input Setup Time
tDS
0.48
-
0.54
-
0.6
-
0.8
-
1.1
-
ns
4,5,6
DQ and DM Input Hold Time
tDH
0.48
-
0.54
-
0.6
-
0.8
-
1.1
-
ns
4,5,6
DQ and DM Input Pulse Width
tDIPW
1.4
-
1.6
-
1.6
-
1.6
-
2.2
-
ns
7
Address and Control Input Setup Time
tIS
0.9
-
1.0
-
1.1
-
1.3
-
1.5
-
ns
6,8,9
Address and Control Input Hold Time
tIH
0.9
-
1.0
-
1.1
-
1.3
-
1.5
-
ns
6,8,9
Address and Control Input Pulse Width
tIPW
2.2
-
2.2
-
2.2
-
2.6
-
3.0
-
ns
7
DQ & DQS Low-impedance time from
CK, CK
tLZ
1
-
1.0
-
1.0
-
1.0
-
1.0
-
ns
10
DQ & DQS High-impedance time from
CK, CK
tHZ
-
5.0
-
5.0
-
5.0
-
6.0
-
7.0
ns
10
DQS - DQ Skew
tDQSQ
-
0.4
-
0.5
-
0.5
-
0.6
-
0.7
ns
11
DQ / DQS output hold time from DQS
tQH
tHP -
tQHS
-
tHP -
tQHS
-
tHP -
tQHS
-
tHP -
tQHS
-
tHP -
tQHS
-
ns
2
Data Hold Skew Factor
tQHS
-
0.5
-
0.5
-
0.65
-
0.75
-
1.0
ns
2
Write Command to 1st DQS Latching
Transition
tDQSS
0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS Input High-Level Width
tDQSH
0.4
-
0.4
-
0.4
-
0.4
-
0.4
-
tCK
DQS Input Low-Level Width
tDQSL
0.4
-
0.4
-
0.4
-
0.4
-
0.4
-
tCK
DQS Falling Edge of CK Setup Time
tDSS
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
tCK
DQS Falling Edge Hold Time from CK
tDSH
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
tCK
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相關代理商/技術參數(shù)
參數(shù)描述
H5MS5162DFR-L3M 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM
H5MS5162EFR 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM)
H5MS5162EFR-J3M 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes
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