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參數(shù)資料
| 型號： | H5MS5162DFR-K3M |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA60 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60 |
| 文件頁數(shù)： | 49/62頁 |
| 文件大?。?/td> | 1314K |
| 代理商： | H5MS5162DFR-K3M |
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Rev 1.3 / Apr. 2009
53
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
Extended Mode Register
The Extended Mode Register contains the specific features of self refresh operation of the Mobile DDR SDRAM.
The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA1=1 and BA0=0) and
will retain the stored information until it is reprogrammed, the device is put in Deep Power-Down mode, or the device
loses power. The Extended Mode Register should be loaded when all Banks are idle and no bursts are in progress, and
subsequent operation should only be initiated after tMRD. Violating these requirements will result in unspecified opera-
tion.
The Extended Mode Register is written by asserting low on CS, RAS, CAS, WE and high on BA0. The state of address
pins A0 ~ A12 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode regis-
ter. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the con-
troller must wait the specified time before initiating any subsequent operation. Violating either of these requirements
will result in unspecified operation.
This register includes the selection of partial array to be refreshed (full array, half array, quarter array, etc.). The
extended mode register set must be done before any activate command after the power up sequence. Any contents of
the mode register be altered by re-programming the mode register through the execution of extended mode register
set command.
PARTIAL ARRAY SELF REFRESH (PASR)
With PASR, the self refresh may be restricted to a variable portion of the total array. The whole array (default), 1/2
array, 1/4 array, 1/8 array or 1/16 array could be selected.
DRIVE STRENGTH (DS)
The drive strength could be set to full or half via address bits A5, A6 and A7. The half drive strength is intended for
lighter loads or point-to-point environments.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| H5MS5162DFR-L3M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM |
| H5MS5162EFR | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM) |
| H5MS5162EFR-J3M | 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes |
| H5MS5162FFR-E3M | 制造商:SK Hynix Inc 功能描述: |
| H5N1503P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching |
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