- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223868 > H5MS5162DFR-K3M (HYNIX SEMICONDUCTOR INC) 32M X 16 DDR DRAM, 0.5 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號(hào)： | H5MS5162DFR-K3M |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.5 ns, PBGA60 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60 |
| 文件頁數(shù)： | 31/62頁 |
| 文件大小： | 1314K |
| 代理商： | H5MS5162DFR-K3M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
Rev 1.3 / Apr. 2009
37
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
READ to PRECHARGE
A Read burst may be followed by or truncated with a PRECHARGE command to the same bank (provided Auto Pre-
charge was not activated). The PRECHARGE command should be issued X cycles after the READ command, where X
equal the number of desired data-out element pairs.
Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
Note that part of the row precharge time is hidden during the access of the last data-out elements.In the case of a
Read being executed to completion, a PRECHARGE command issued at the optimum time (as described above) pro-
vides the same operation that would result from Read burst with Auto Precharge enabled.
The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at
the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to
truncate bursts.
READ to PRECHARGE
/CLK
CLK
Do
n
Do
n
READ
NOP
PRE
NOP
ACT
BA,
Col
n
CL =3
CL =2
Don't Care
1) DO
n = Data Out from column n
2) Cases shown are either uninterrupted burst of 4, or interrupted bursts of 8
3) Shown with nominal tAC, tDQSCK and tDQSQ
4) Precharge may be applied at (BL / 2) tCK after the READ command.
5) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks.
6) The ACTIVE command may be applied if tRC has been met.
Command
Address
DQS
DQ
DQS
DQ
Bank
(A or All)
BA,
Row
tRP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| H6101NL | DATACOM TRANSFORMER FOR GENERAL PURPOSE APPLICATION(S) |
| H6E1PC03130001 | 105 CONTACT(S), MULTIWAY RACK AND PANEL CONN, CRIMP, PLUG |
| H6E1PX03130001 | 105 CONTACT(S), MULTIWAY RACK AND PANEL CONN, PLUG |
| H6E2PC03130001 | MULTIWAY RACK AND PANEL CONN, CRIMP, PLUG |
| H6E2PX03130001 | MULTIWAY RACK AND PANEL CONN, PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| H5MS5162DFR-L3M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM |
| H5MS5162EFR | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM) |
| H5MS5162EFR-J3M | 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes |
| H5MS5162FFR-E3M | 制造商:SK Hynix Inc 功能描述: |
| H5N1503P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。