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Rev 1.3 / Apr. 2009
4
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
DESCRIPTION
The Hynix H5MS5162DFR Series is 536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile
DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones
with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 8,388,608
x16.
The HYNIX H5MS5162DFR series uses a double-data-rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2
n prefetch architecture with an interface designed to transfer two data per clock
cycle at the I/O pins.
The Hynix H5MS5162DFR Series offers fully synchronous operations referenced to both rising and falling edges of the
clock. While all address and control inputs are latched on the rising edges of the CK (Mobile DDR SDRAM operates
from a differential clock
: the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK),
data, data strobe and data mask inputs are sampled on both rising and falling edges of it (
Input data is registered on
both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK). The data
paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. All input voltage levels are compatible
with LVCMOS.
Read and write accesses to the Low Power DDR SDRAM (Mobile DDR SDRAM) are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with
the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits reg-
istered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the bank and the starting column location
for the burst access.
The Low Power DDR SDRAM (Mobile DDR SDRAM) provides for programmable read or write bursts of 2, 4 or 8 loca-
tions. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end
of the burst access.
As with standard SDRAM, the pipelined and multibank architecture of Low Power DDR SDRAM (Mobile DDR SDRAM)
allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation
times.
The Low Power DDR SDRAM (Mobile DDR SDRAM) also provides for special programmable Self Refresh options which
are Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array) and Temperature Compensated Self Refresh.
A burst of Read or Write cycles in progress can be interrupted and replaced by a new burst Read or Write command on
any cycle (this pipelined design is not restricted by a 2N rule). Only Read bursts in progress with auto precharge disa-
bled can be terminated by a burst terminate command. Burst Terminate command is undefined and should not be
used for Read with Autoprecharge enabled and for Write bursts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| H6101NL | DATACOM TRANSFORMER FOR GENERAL PURPOSE APPLICATION(S) |
| H6E1PC03130001 | 105 CONTACT(S), MULTIWAY RACK AND PANEL CONN, CRIMP, PLUG |
| H6E1PX03130001 | 105 CONTACT(S), MULTIWAY RACK AND PANEL CONN, PLUG |
| H6E2PC03130001 | MULTIWAY RACK AND PANEL CONN, CRIMP, PLUG |
| H6E2PX03130001 | MULTIWAY RACK AND PANEL CONN, PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| H5MS5162DFR-L3M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM |
| H5MS5162EFR | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM) |
| H5MS5162EFR-J3M | 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes |
| H5MS5162FFR-E3M | 制造商:SK Hynix Inc 功能描述: |
| H5N1503P | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching |
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