參數(shù)資料
型號(hào)： H5MS5162DFR-K3M
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 0.5 ns, PBGA60
封裝： 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60
文件頁數(shù)： 24/62頁
文件大?。?/td> 1314K
代理商： H5MS5162DFR-K3M
Rev 1.3 / Apr. 2009
30
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
READ / WRITE COMMAND
The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and
address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being
accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open
for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued.
The Mobile DDR drives the DQS during read operations. The initial low state of the DQS is known as the read preamble
and the last data-out element is coincident with the read postamble. DQS is edge-aligned with read data. Upon com-
pletion of a burst, assuming no new READ commands have been initiated, the I/O's will go high-Z.
The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank
and address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used.If auto precharge is selected, the row being
accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open
for subsequent access. Input data appearing on the data bus, is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be
written to the memory; if the DM signal is registered high, the corresponding data-inputs will be ignored, and a write
will not be executed to that byte/column location. The memory controller drives the DQS during write operations. The
initial low state of the DQS is known as the write preamble and the low state following the last data-in element is write
postamble. Upon completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z
and any additional input data will be ignored.
READ / WRITE COMMAND
Don't Care
CA
BA
High to enable
Auto Precharge
Low to disable
Auto Precharge
Read Com m and
W rite Com m and
CA
BA
CLK
CKE
CLK
CKE
(High)
CS
A0~ A9
W E
CAS
A10
RAS
BA0, BA1
CS
A0~ A9
W E
CAS
A10
RAS
BA0, BA1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
H5MS5162DFR-L3M 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM
H5MS5162EFR 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM)
H5MS5162EFR-J3M 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes
H5MS5162FFR-E3M 制造商:SK Hynix Inc 功能描述:
H5N1503P 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching
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