參數(shù)資料
型號： H5MS5162DFR-K3M
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： 32M X 16 DDR DRAM, 0.5 ns, PBGA60
封裝： 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, FBGA-60
文件頁數(shù)： 57/62頁
文件大小： 1314K
代理商： H5MS5162DFR-K3M
Rev 1.3 / Apr. 2009
60
11
Mobile DDR SDRAM 512Mbit (32M x 16bit)
H5MS5162DFR Series
POWER-UP AND INITIALIZATION SEQUENCES
Mobile DDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other thank
those specified may result in undefined operation. If there is any interruption to the device power, the initialization
routine should be followed. The steps to be followed for device initialization are listed below.
●
● Step1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up simulta-
neously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are from
the same power source. Also assert and hold CLOCK ENABLE (CKE) to a LVCMOS logic high level.
●
● Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply stable
clock.
●
● Step 3: There must be at least 200us of valid clocks before any command may be given to the DRAM. During this
time NOP or DESELECT commands must be issued on the command bus.
●
● Step 4: Issue a PRECHARGE ALL command.
●
● Step 5: Provide NOPs or DESELECT commands for at least tRP time.
●
● Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Issue
the second AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time.
Note as part of the initialization sequence there must be two auto refresh commands issued. The typical
flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.
●
● Step 7: Using the MRS command, load the base mode register. Set the desired operating modes.
●
● Step 8: Provide NOPs or DESELECT commands for at least tMRD time.
●
● Step 9: Using the MRS command, program the extended mode register for the desired operating modes. Note the
order of the base and extended mode register programming is not important.
●
● Step 10: Provide NOP or DESELCT commands for at least tMRD time.
●
● Step 11: The DRAM has been properly initialized and is ready for any valid command.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
H5MS5162DFR-L3M 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb (32Mx16bit) Mobile DDR SDRAM
H5MS5162EFR 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM)
H5MS5162EFR-J3M 制造商:SK Hynix Inc 功能描述:SDRAM MOBILE DDR 512MB (X16) 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory C 制造商:SK Hynix Inc 功能描述:SDRAM, MOBILE DDR, 512MB (X16), 60FBGA, Memory Type:DRAM - Synchronous, Memory Configuration:32M x 16, Memory Case Style:FBGA, No. of Pins:60, IC Interface Type:LVCMOS, Operating Temperature Min:-30C, Operating Temperature Max:85C, , RoHS Compliant: Yes
H5MS5162FFR-E3M 制造商:SK Hynix Inc 功能描述:
H5N1503P 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Silicon N Channel MOS FET High Speed Power Switching
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