參數(shù)資料
型號： EVAL-ADUC7029QSZ
廠商： Analog Devices Inc
文件頁數(shù)： 70/104頁
文件大?。?/td> 0K
描述： EVAL DEV SYSTEM FOR ADUC7029
設(shè)計資源： ADuC70xx Serial Download Protocol
ADuC7029 Dev System Schematic
標準包裝： 1
系列： *
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 68 of 104
Table 78. GPIO Pin Function Descriptions
Configuration
Port
Pin
00
01
10
11
0
P0.0
GPIO
CMP
MS0
PLAI[7]
P0.1
GPIO
PWM2H
BLE
P0.2
GPIO
PWM2L
BHE
P0.3
GPIO
TRST
A16
ADCBUSY
P0.4
GPIO/IRQ0
PWMTRIP
MS1
PLAO[1]
P0.5
GPIO/IRQ1
ADCBUSY
MS2
PLAO[2]
P0.6
GPIO/T1
MRST
PLAO[3]
P0.7
GPIO
ECLK/XCLK1
SIN
PLAO[4]
1
P1.0
GPIO/T1
SIN
SCL0
PLAI[0]
P1.1
GPIO
SOUT
SDA0
PLAI[1]
P1.2
GPIO
RTS
SCL1
PLAI[2]
P1.3
GPIO
CTS
SDA1
PLAI[3]
P1.4
GPIO/IRQ2
RI
SCLK
PLAI[4]
P1.5
GPIO/IRQ3
DCD
MISO
PLAI[5]
P1.6
GPIO
DSR
MOSI
PLAI[6]
P1.7
GPIO
DTR
CS
PLAO[0]
2
P2.0
GPIO
CONVSTART2
SOUT
PLAO[5]
P2.1
GPIO
PWM0H
WS
PLAO[6]
P2.2
GPIO
PWM0L
RS
PLAO[7]
P2.3
GPIO
AE
P2.4
GPIO
PWM0H
MS0
P2.5
GPIO
PWM0L
MS1
P2.6
GPIO
PWM1H
MS2
P2.7
GPIO
PWM1L
MS3
3
P3.0
GPIO
PWM0H
AD0
PLAI[8]
P3.1
GPIO
PWM0L
AD1
PLAI[9]
P3.2
GPIO
PWM1H
AD2
PLAI[10]
P3.3
GPIO
PWM1L
AD3
PLAI[11]
P3.4
GPIO
PWM2H
AD4
PLAI[12]
P3.5
GPIO
PWM2L
AD5
PLAI[13]
P3.6
GPIO
PWMTRIP
AD6
PLAI[14]
P3.7
GPIO
PWMSYNC
AD7
PLAI[15]
4
P4.0
GPIO
AD8
PLAO[8]
P4.1
GPIO
AD9
PLAO[9]
P4.2
GPIO
AD10
PLAO[10]
P4.3
GPIO
AD11
PLAO[11]
P4.4
GPIO
AD12
PLAO[12]
P4.5
GPIO
AD13
PLAO[13]
P4.6
GPIO
AD14
PLAO[14]
P4.7
GPIO
AD15
PLAO[15]
1
When configured in Mode 1, P0.7 is ECLK by default, or core clock output. To
configure it as a clock input, the MDCLK bits in PLLCON must be set to 11.
2
The CONVSTART signal is active in all modes of P2.0.
Table 79. GPxCON Registers
Name
Address
Default Value
Access
GP0CON
0xFFFFF400
0x00000000
R/W
GP1CON
0xFFFFF404
0x00000000
R/W
GP2CON
0xFFFFF408
0x00000000
R/W
GP3CON
0xFFFFF40C
0x00000000
R/W
GP4CON
0xFFFFF410
0x00000000
R/W
GPxCON are the Port x control registers, which select the
function of each pin of Port x as described in Table 80.
Table 80. GPxCON MMR Bit Descriptions
Bit
Description
31:30
Reserved.
29:28
Select function of the Px.7 pin.
27:26
Reserved.
25:24
Select function of the Px.6 pin.
23:22
Reserved.
21:20
Select function of the Px.5 pin.
19:18
Reserved.
17:16
Select function of the Px.4 pin.
15:14
Reserved.
13:12
Select function of the Px.3 pin.
11:10
Reserved.
9:8
Select function of the Px.2 pin.
7:6
Reserved.
5:4
Select function of the Px.1 pin.
3:2
Reserved.
1:0
Select function of the Px.0 pin.
Table 81. GPxPAR Registers
Name
Address
Default Value
Access
GP0PAR
0xFFFFF42C
0x20000000
R/W
GP1PAR
0xFFFFF43C
0x00000000
R/W
GPxPAR program the parameters for Port 0 and Port 1. Note that
the GPxDAT MMR must always be written after changing the
GPxPAR MMR.
Table 82. GPxPAR MMR Bit Descriptions
Bit
Description
31
Reserved.
30:29
Drive strength Px.7.
28
Pull-Up Disable Px.7.
27
Reserved.
26:25
Drive strength Px.6.
24
Pull-Up Disable Px.6.
23
Reserved.
22:21
Drive strength Px.5.
20
Pull-Up Disable Px.5.
19
Reserved.
18:17
Drive strength Px.4.
16
Pull-Up Disable Px.4.
15
Reserved.
14:13
Drive strength Px.3.
12
Pull-Up Disable Px.3.
11
Reserved.
10:9
Drive strength Px.2.
8
Pull-Up Disable Px.2.
7
Reserved.
6:5
Drive strength Px.1.
4
Pull-Up Disable Px.1.
3
Reserved.
2:1
Drive strength Px.0.
0
Pull-Up Disable Px.0.
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