- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗17109 > EVAL-ADUC7029QSZ (Analog Devices Inc)EVAL DEV SYSTEM FOR ADUC7029 PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | EVAL-ADUC7029QSZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 2/104闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | EVAL DEV SYSTEM FOR ADUC7029 |
| 瑷�(sh猫)瑷堣硣婧愶細 | ADuC70xx Serial Download Protocol ADuC7029 Dev System Schematic |
| 妯欐簴鍖呰锛� | 1 |
| 绯诲垪锛� | * |
绗�1闋�鐣跺墠绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 10 of 104
SPECIFICATIONS
AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = 40掳C to +125掳C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
Eight acquisition clocks and fADC/2
ADC Power-Up Time
5
渭s
DC Accuracy1, 2
Resolution
12
Bits
Integral Nonlinearity
卤0.6
卤1.5
LSB
2.5 V internal reference
卤1.0
LSB
1.0 V external reference
Differential Nonlinearity3, 4
卤0.5
+1/0.9
LSB
2.5 V internal reference
+0.7/0.6
LSB
1.0 V external reference
DC Code Distribution
1
LSB
ADC input is a dc voltage
ENDPOINT ERRORS5
Offset Error
卤1
卤2
LSB
Offset Error Match
卤1
LSB
Gain Error
卤2
卤5
LSB
Gain Error Match
卤1
LSB
DYNAMIC PERFORMANCE
fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS
Signal-to-Noise Ratio (SNR)
69
dB
Includes distortion and noise components
Total Harmonic Distortion (THD)
78
dB
Peak Harmonic or Spurious Noise
(PHSN)
75
dB
Channel-to-Channel Crosstalk
80
dB
Measured on adjacent channels
ANALOG INPUT
Input Voltage Ranges
Differential Mode
V
Single-Ended Mode
0 to VREF
V
Leakage Current
卤1
卤6
A
Input Capacitance
20
pF
During ADC acquisition
ON-CHIP VOLTAGE REFERENCE
0.47 F from VREF to AGND
Output Voltage
2.5
V
Accuracy
卤5
mV
TA = 25掳C
Reference Temperature Coefficient
卤40
ppm/掳C
Power Supply Rejection Ratio
75
dB
Output Impedance
70
TA = 25掳C
Internal VREF Power-On Time
1
ms
EXTERNAL REFERENCE INPUT
Input Voltage Range
0.625
AVDD
V
DAC CHANNEL SPECIFICATIONS
RL = 5 k, CL = 100 pF
DC Accuracy7
Resolution
12
Bits
Relative Accuracy
卤2
LSB
Differential Nonlinearity
卤1
LSB
Guaranteed monotonic
Offset Error
卤15
mV
2.5 V internal reference
Gain Error8
卤1
%
Gain Error Mismatch
0.1
%
% of full scale on DAC0
ANALOG OUTPUTS
Output Voltage Range_0
0 to DACREF
V
DACREF range: DACGND to DACVDD
Output Voltage Range_1
0 to 2.5
V
Output Voltage Range_2
0 to DACVDD
V
Output Impedance
2
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| EVAL-ADUC824QSZ | KIT DEV QUICK START ADUC824 |
| RPS-1K-22-18/2.0-9 | HEAT SHRINK SLEEVE |
| EBM31DCMN | CONN EDGECARD 62POS .156 WW |
| REC5-243.3DRWZ/H/B | CONV DC/DC 5W 9-36VIN +/-3.3V |
| ADR06WARZ-R7 | IC VREF SERIES PREC 3V 8SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| EVAL-ADUC7029QSZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:Silicon Manufacturer:Analog Devices C |
| EVAL-ADUC7032QSPZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:EVAL BD FOR ADUC7032 - Bulk |
| EVAL-ADUC7033QSPZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:QUICK START DEVELOPMENT SYSTEM - Bulk |
| EVAL-ADUC7034QSPZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:EVALUATION BOARD - Boxed Product (Development Kits) |
| EVAL-ADUC7036QSPZ | 鍔熻兘鎻忚堪:BOARD EVAL FOR ADUC7036 RoHS:鏄� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 瑭曚及婕旂ず鏉垮拰濂椾欢 绯诲垪:QuickStart™ PLUS 濂椾欢 妯欐簴鍖呰:1 绯诲垪:PSoC® 涓昏鐩殑:闆绘簮绠＄悊锛岀啽绠＄悊 宓屽叆寮�:- 宸茬敤 IC / 闆朵欢:- 涓昏灞€�:- 娆¤灞€�:- 宸蹭緵鐗╁搧:鏉�锛孋D锛岄浕婧� |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
