- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17109 > EVAL-ADUC7029QSZ (Analog Devices Inc)EVAL DEV SYSTEM FOR ADUC7029 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADUC7029QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 48/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL DEV SYSTEM FOR ADUC7029 |
| 設(shè)計(jì)資源： | ADuC70xx Serial Download Protocol ADuC7029 Dev System Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁當(dāng)前第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 48 of 104
Table 22. ADCCN MMR Bit Designation
Bit
Value
Description
7:5
Reserved.
4:0
Negative channel selection bits.
00000
ADC0.
00001
ADC1.
00010
ADC2.
00011
ADC3.
00100
ADC4.
00101
ADC5.
00110
ADC6.
00111
ADC7.
01000
ADC8.
01001
ADC9.
01010
ADC10.
01011
ADC11.
01100
DAC0/ADC12.
01101
DAC1/ADC13.
01110
DAC2/ADC14.
01111
DAC3/ADC15.
10000
Internal reference (self-diagnostic feature).
Others
Reserved.
Table 23. ADCSTA Register
Name
Address
Default Value
Access
ADCSTA
0xFFFF050C
0x00
R
ADCSTA is an ADC status register that indicates when an ADC
conversion result is ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the ADCBUSY
pin. This pin is high during a conversion. When the conversion
is finished, ADCBUSY goes back low. This information can be
available on P0.5 (see the General-Purpose Input/Output
section) if enabled in the ADCCON register.
Table 24. ADCDAT Register
Name
Address
Default Value
Access
ADCDAT
0xFFFF0510
0x00000000
R
ADCDAT is an ADC data result register. It holds the 12-bit
ADC result as shown in Figure 51.
Table 25. ADCRST Register
Name
Address
Default Value
Access
ADCRST
0xFFFF0514
0x00
R/W
ADCRST resets the digital interface of the ADC. Writing any value
to this register resets all the ADC registers to their default values.
Table 26. ADCGN Register
Name
Address
Default Value
Access
ADCGN
0xFFFF0530
0x0200
R/W
ADCGN is a 10-bit gain calibration register.
Table 27. ADCOF Register
Name
Address
Default Value
Access
ADCOF
0xFFFF0534
0x0200
R/W
ADCOF is a 10-bit offset calibration register.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three modes: differential, pseudo
differential, and single-ended.
Differential Mode
The ADuC7019/20/21/22/24/25/26/27/28/29 each contain a
successive approximation ADC based on two capacitive DACs.
Figure 54 and Figure 55 show simplified schematics of the ADC
in acquisition and conversion phase, respectively. The ADC
comprises control logic, a SAR, and two capacitive DACs. In
Figure 54 (the acquisition phase), SW3 is closed and SW1 and
SW2 are in Position A. The comparator is held in a balanced
condition, and the sampling capacitor arrays acquire the
differential signal on the input.
04955-
017
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
Figure 54. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 55, SW3
opens, and then SW1 and SW2 move to Position B. This causes
the comparator to become unbalanced. Both inputs are discon-
nected once the conversion begins. The control logic and the
charge redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to bring
the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC output code. The output
impedances of the sources driving the VIN+ and VIN– input
voltage pins must be matched; otherwise, the two inputs have
different settling times, resulting in errors.
04955-
018
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
Figure 55. ADC Conversion Phase
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EVAL-ADUC824QSZ | KIT DEV QUICK START ADUC824 |
| RPS-1K-22-18/2.0-9 | HEAT SHRINK SLEEVE |
| EBM31DCMN | CONN EDGECARD 62POS .156 WW |
| REC5-243.3DRWZ/H/B | CONV DC/DC 5W 9-36VIN +/-3.3V |
| ADR06WARZ-R7 | IC VREF SERIES PREC 3V 8SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7029QSZ | 制造商:Analog Devices 功能描述:Silicon Manufacturer:Analog Devices C |
| EVAL-ADUC7032QSPZ | 制造商:Analog Devices 功能描述:EVAL BD FOR ADUC7032 - Bulk |
| EVAL-ADUC7033QSPZ | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk |
| EVAL-ADUC7034QSPZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) |
| EVAL-ADUC7036QSPZ | 功能描述:BOARD EVAL FOR ADUC7036 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:QuickStart™ PLUS 套件 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。