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| 型號： | EVAL-ADUC7029QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 58/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL DEV SYSTEM FOR ADUC7029 |
| 設(shè)計資源： | ADuC70xx Serial Download Protocol ADuC7029 Dev System Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 57 of 104
Linearity degradation near ground and AVDD is caused by satu-
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is illustrated in Figure 64.
The dotted line in Figure 64 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 64 represents a transfer function
in 0-to-AVDD mode only. In 0-to-VREF or 0-to-DACREF mode
(with VREF < AVDD or DACREF < AVDD), the lower nonlinearity is
similar. However, the upper portion of the transfer function
follows the ideal line right to the end (VREF in this case, not AVDD),
showing no signs of endpoint linearity errors.
0
495
5-
02
4
AVDD
AVDD – 100mV
100mV
0x00000000
0x0FFF0000
Figure 64. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in
Figure 64 get worse as a function of output loading. Most
of the ADuC7019/20/21/22/24/25/26/27/28/29 data sheet
specifications assume a 5 kΩ resistive load to ground at the
DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom (respectively)
of Figure 64 become larger. With larger current demands, this
can significantly limit output voltage swing.
POWER SUPPLY MONITOR
The power supply monitor regulates the IOVDD supply on the
ADuC7019/20/21/22/24/25/26/27/28/29. It indicates when the
IOVDD supply pin drops below one of two supply trip points.
The monitor function is controlled via the PSMCON register.
If enabled in the IRQEN or FIQEN register, the monitor
interrupts the core using the PSMI bit in the PSMCON MMR.
This bit is immediately cleared after CMP goes high.
This monitor function allows the user to save working registers
to avoid possible data loss due to low supply or brown-out
conditions. It also ensures that normal code execution does
not resume until a safe supply level is established.
Table 53. PSMCON Register
Name
Address
Default Value
Access
PSMCON
0xFFFF0440
0x0008
R/W
Table 54. PSMCON MMR Bit Descriptions
Bit
Name
Description
3
CMP
Comparator bit. This is a read-only bit that
directly reflects the state of the comparator.
Read 1 indicates that the IOVDD supply is above
its selected trip point or that the PSM is in
power-down mode. Read 0 indicates that the
IOVDD supply is below its selected trip point. This
bit should be set before leaving the interrupt
service routine.
2
TP
Trip point selection bit. 0 = 2.79 V, 1 = 3.07 V.
1
PSMEN
Power supply monitor enable bit. Set to 1 to
enable the power supply monitor circuit. Cleared
to 0 to disable the power supply monitor circuit.
0
PSMI
Power supply monitor interrupt bit. This bit is set
high by the MicroConverter after CMP goes low,
indicating low I/O supply. The PSMI bit can be
used to interrupt the processor. After CMP
returns high, the PSMI bit can be cleared by
writing a 1 to this location. A 0 write has no
effect. There is no timeout delay; PSMI can be
immediately cleared after CMP goes high.
COMPARATOR
The ADuC7019/20/21/22/24/25/26/27/28/29 integrate voltage
comparators. The positive input is multiplexed with ADC2, and
the negative input has two options: ADC3 and DAC0. The output
of the comparator can be configured to generate a system inter-
rupt, be routed directly to the programmable logic array, start
an ADC conversion, or be on an external pin, CMPOUT, as
shown in Figure 65.
04
95
5-
02
5
MUX
IRQ
MUX
DAC0
ADC2/CMP0
ADC3/CMP1
P0.0/CMPOUT
Figure 65. Comparator
Note that because the ADuC7022, ADuC7025, and ADu7027
parts do not support a DAC0 output, it is not possible to use
DAC0 as a comparator input on these parts.
Hysteresis
Figure 66 shows how the input offset voltage and hysteresis
terms are defined.
04
95
5-
0
63
CMPOUT
CMP0
VH
VOS
Figure 66. Comparator Hysteresis Transfer Function
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