參數(shù)資料
型號: EVAL-ADUC7029QSZ
廠商: Analog Devices Inc
文件頁數(shù): 32/104頁
文件大?。?/td> 0K
描述: EVAL DEV SYSTEM FOR ADUC7029
設(shè)計(jì)資源: ADuC70xx Serial Download Protocol
ADuC7029 Dev System Schematic
標(biāo)準(zhǔn)包裝: 1
系列: *
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 33 of 104
ADUC7029
BOTTOM VIEW
(Not to Scale)
7
4
5
6
3
2
1
A
B
C
D
E
F
G
04955-
088
Figure 27. 49-Ball CSP_BGA Pin Configuration (ADuC7029)
Table 15. Pin Function Descriptions (ADuC7029)
Ball No.
Mnemonic
Description
A1
ADC3/CMP1
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
A2
ADC1
Single-Ended or Differential Analog Input 1.
A3
ADC0
Single-Ended or Differential Analog Input 0.
A4
AVDD
3.3 V Analog Power.
A5
VREF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 F capacitor when using the
internal reference.
A6
P1.0/T1/SPM0/PLAI[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
A7
P1.1/SPM1/PLAI[1]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
B1
ADC6
Single-Ended or Differential Analog Input 6.
B2
ADC5
Single-Ended or Differential Analog Input 5.
B3
ADC4
Single-Ended or Differential Analog Input 4.
B4
AGND
Analog Ground. Ground reference point for the analog circuitry.
B5
DACREF
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
B6
P1.4/SPM4/PLAI[4]/IRQ2
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
B7
P1.3/SPM3/PLAI[3]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
C1
GNDREF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
C2
AGND
Analog Ground. Ground reference point for the analog circuitry.
C3
ADC2/CMP0
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
C4
IOGND
Ground for GPIO (see Table 78). Typically connected to DGND.
C5
P1.2/SPM2/PLAI[2]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
C6
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
C7
P1.5/SPM5/PLAI[5]/IRQ3
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
D1
DAC0/ADC12
DAC0 Voltage Output/ADC Input 12.
D2
DAC3/ADC15
DAC3 Voltage Output/ADC Input 15.
D3
DAC1/ADC13
DAC1 Voltage Output/ADC Input 13.
D4
P3.3/PWM1L/PLAI[11]
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable
Logic Array Input Element 11.
D5
P3.4/PWM2H/PLAI[12]
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable
Logic Array Input 12.
D6
P3.6/PWMTRIP/PLAI[14]
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array
Input Element 14.
D7
P1.7/SPM7/PLAO[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
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