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| 型號： | EVAL-ADUC7029QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/104頁 |
| 文件大小： | 0K |
| 描述： | EVAL DEV SYSTEM FOR ADUC7029 |
| 設(shè)計資源： | ADuC70xx Serial Download Protocol ADuC7029 Dev System Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 46 of 104
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
The top four bits are the sign bits. The 12-bit result is placed
from Bit 16 to Bit 27, as shown in Figure 51. Again, it should be
noted that, in fully differential mode, the result is represented in
twos complement format. In pseudo differential and single-
ended modes, the result is represented in straight binary format.
04
95
5-
01
4
SIGN BITS
12-BIT ADC RESULT
31
27
16 15
0
Figure 51. ADC Result Format
The same format is used in DACxDAT, simplifying the software.
Current Consumption
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 μA. The internal reference
adds 140 μA. During conversion, the extra current is 0.3 μA
multiplied by the sampling frequency (in kilohertz (kHz)).
Figure 43 shows the current consumption vs. the sampling
frequency of the ADC.
Timing
Figure 52 gives details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight clocks
and the clock divider is 2. The number of extra clocks (such as
bit trial or write) is set to 19, which gives a sampling rate of
774 kSPS. For conversion on the temperature sensor, the ADC
acquisition time is automatically set to 16 clocks, and the ADC
clock divider is set to 32. When using multiple channels,
including the temperature sensor, the timing settings revert to
the user-defined settings after reading the temperature sensor
channel.
0
495
5-
015
ADC CLOCK
ACQ
BIT TRIAL
DATA
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
WRITE
CONVSTART
ADCBUSY
ADCDAT
Figure 52. ADC Timing
ADuC7019
The ADuC7019 is identical to the ADuC7020 except for one
buffered ADC channel, ADC3, and it has only three DACs. The
output buffer of the fourth DAC is internally connected to the
ADC3 channel as shown in Figure 53.
04
95
5-
016
1MSPS
12-BIT ADC
12-BIT
DAC
MUX
ADC3
ADC15
DAC3
ADuC7019
Figure 53. ADC3 Buffered Input
Note that the DAC3 output pin must be connected to a 10 nF
capacitor to AGND. This channel should be used to measure dc
voltages only. ADC calibration may be necessary on this channel.
MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs
described in this section.
Table 17. ADCCON Register
Name
Address
Default Value
Access
ADCCON
0xFFFF0500
0x0600
R/W
ADCCON is an ADC control register that allows the programmer
to enable the ADC peripheral, select the mode of operation of
the ADC (in single-ended mode, pseudo differential mode, or
fully differential mode), and select the conversion type. This
MMR is described in Table 18.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7029QSZ | 制造商:Analog Devices 功能描述:Silicon Manufacturer:Analog Devices C |
| EVAL-ADUC7032QSPZ | 制造商:Analog Devices 功能描述:EVAL BD FOR ADUC7032 - Bulk |
| EVAL-ADUC7033QSPZ | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk |
| EVAL-ADUC7034QSPZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) |
| EVAL-ADUC7036QSPZ | 功能描述:BOARD EVAL FOR ADUC7036 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:QuickStart™ PLUS 套件 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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