參數(shù)資料
型號(hào)： EVAL-ADUC7029QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 31/104頁(yè)
文件大?。?/td> 0K
描述： EVAL DEV SYSTEM FOR ADUC7029
設(shè)計(jì)資源： ADuC70xx Serial Download Protocol
ADuC7029 Dev System Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 32 of 104
Ball No.
Mnemonic
Description
D7
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
D8
IOVDD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
E1
DAC3/ADC15
DAC3 Voltage Output/ADC Input 15.
E2
DAC2/ADC14
DAC2 Voltage Output/ADC Input 14.
E3
DAC1/ADC13
DAC1 Voltage Output/ADC Input 13.
E4
P3.0/PWM0H/PLAI[8]
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable
Logic Array Input Element 8.
E5
P3.2/PWM1H/PLAI[10]
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable
Logic Array Input Element 10.
E6
P1.5/SPM5/PLAI[5]/IRQ3
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
E7
P3.7/PWMSYNC/PLAI[15]
General-Purpose Input and Output Port 3.7/PWM Synchronization/Programmable Logic
Array Input Element 15.
E8
XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
F1
P4.6/PLAO[14]
General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
F2
TDI
JTAG Test Port Input, Test Data In. Debug and download access.
F3
DAC0/ADC12
DAC0 Voltage Output/ADC Input 12.
F4
P3.1/PWM0L/PLAI[9]
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable
Logic Array Input Element 9.
F5
P3.3/PWM1L/PLAI[11]
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable
Logic Array Input Element 11.
F6
RST
Reset Input, Active Low.
F7
P0.7/ECLK/XCLK/SPM8/PLAO[4]
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External
Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array
Output Element 4.
F8
XCLKO
Output from the Crystal Oscillator Inverter.
G1
BM/P0.0/CMPOUT/PLAI[7]
Multifunction I/O Pin. Boot mode. The ADuC7028 enters UART download mode if BM is low
at reset and executes code if BM is pulled high at reset through a 1 k resistor/General-
Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
G2
P4.7/PLAO[15]
General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
G3
TMS
JTAG Test Port Input, Test Mode Select. Debug and download access.
G4
TDO
JTAG Test Port Output, Test Data Out. Debug and download access.
G5
P0.3/TRST/ADCBUSY
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal
Output.
G6
P3.4/PWM2H/PLAI[12]
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable
Logic Array Input 12.
G7
P3.5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable
Logic Array Input Element 13.
G8
P2.0/SPM9/PLAO[5]/CONVSTART
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable
Logic Array Output Element 5/Start Conversion Input Signal for ADC.
H1
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
H2
TCK
JTAG Test Port Input, Test Clock. Debug and download access.
H3
IOGND
Ground for GPIO (see Table 78). Typically connected to DGND.
H4
IOVDD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
H5
LVDD
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 F
capacitor to DGND only.
H6
DGND
Ground for Core Logic.
H7
IRQ0/P0.4/PWMTRIP/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
H8
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.
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