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Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 15 of 104
Table 4. I2C Timing in Fast Mode (400 kHz)
Slave
Master
Parameter
Description
Min
Max
Typ
Unit
tL
SCL low pulse width1
200
1360
ns
tH
SCL high pulse width1
100
1140
ns
tSHD
Start condition hold time
300
ns
tDSU
Data setup time
100
740
ns
tDHD
Data hold time
0
400
ns
tRSU
Setup time for repeated start
100
ns
tPSU
Stop condition setup time
100
400
ns
tBUF
Bus-free time between a stop condition and a start condition
1.3
s
tR
Rise time for both SCL and SDA
300
200
ns
tF
Fall time for both SCL and SDA
300
ns
tSUP
Pulse width of spike suppressed
50
ns
1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 67.
Table 5. I2C Timing in Standard Mode (100 kHz)
Slave
Master
Parameter
Description
Min
Max
Typ
Unit
tL
SCL low pulse width1
4.7
渭s
tH
SCL high pulse width1
4.0
ns
tSHD
Start condition hold time
4.0
渭s
tDSU
Data setup time
250
ns
tDHD
Data hold time
0
3.45
渭s
tRSU
Setup time for repeated start
4.7
渭s
tPSU
Stop condition setup time
4.0
渭s
tBUF
Bus-free time between a stop condition and a start condition
4.7
渭s
tR
Rise time for both SCL and SDA
1
渭s
tF
Fall time for both SCL and SDA
300
ns
1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 67.
0
4
955
-054
SDA (I/O)
tBUF
MSB
LSB
ACK
MSB
1
9
8
2鈥�7
1
SCL (I)
PS
STOP
CONDITION
START
CONDITION
S(R)
REPEATED
START
tSUP
tR
tF
tR
tH
tL
tSUP
tDSU
tDHD
tRSU
tDHD
tDSU
tSHD
tPSU
Figure 14. I2C Compatible Interface Timing
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