- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗17109 > EVAL-ADUC7029QSZ (Analog Devices Inc)EVAL DEV SYSTEM FOR ADUC7029 PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | EVAL-ADUC7029QSZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 51/104闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | EVAL DEV SYSTEM FOR ADUC7029 |
| 瑷�(sh猫)瑷堣硣婧愶細 | ADuC70xx Serial Download Protocol ADuC7029 Dev System Schematic |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | * |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�鐣�(d膩ng)鍓嶇51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 50 of 104
Table 28. VCM Ranges
AVDD
VREF
VCM Min
VCM Max
Signal Peak-to-Peak
3.3 V
2.5 V
1.25 V
2.05 V
2.5 V
2.048 V
1.024 V
2.276 V
2.048 V
1.25 V
0.75 V
2.55 V
1.25 V
3.0 V
2.5 V
1.25 V
1.75 V
2.5 V
2.048 V
1.024 V
1.976 V
2.048 V
1.25 V
0.75 V
2.25 V
1.25 V
CALIBRATION
By default, the factory-set values written to the ADC offset
(ADCOF) and gain coefficient registers (ADCGN) yield
optimum performance in terms of end-point errors and
linearity for standalone operation of the part (see the
Specifications section). If system calibration is required, it is
possible to modify the default offset and gain coefficients to
improve end-point errors, but note that any modification to the
factory-set ADCOF and ADCGN values can degrade ADC
linearity performance.
For system offset error correction, the ADC channel input stage
must be tied to AGND. A continuous software ADC conversion
loop must be implemented by modifying the value in ADCOF until
the ADC result (ADCDAT) reads Code 0 to Code 1. If the
ADCDAT value is greater than 1, ADCOF should be decremented
until ADCDAT reads 0 to 1. Offset error correction is done
digitally and has a resolution of 0.25 LSB and a range of
卤3.125% of VREF.
For system gain error correction, the ADC channel input stage
must be tied to VREF. A continuous software ADC conversion
loop must be implemented to modify the value in ADCGN
until the ADC result (ADCDAT) reads Code 4094 to Code 4095.
If the ADCDAT value is less than 4094, ADCGN should be
incremented until ADCDAT reads 4094 to 4095. Similar to the
offset calibration, the gain calibration resolution is 0.25 LSB
with a range of 卤3% of VREF.
TEMPERATURE SENSOR
The ADuC7019/20/21/22/24/25/26/27/28/29 provide voltage
output from on-chip band gap references proportional to
absolute temperature. This voltage output can also be routed
through the front-end ADC multiplexer (effectively an additional
ADC channel input) facilitating an internal temperature sensor
channel, measuring die temperature to an accuracy of 卤3掳C.
The following is an example routine showing how to use the
internal temperature sensor:
int main(void)
{
float a = 0;
short b;
ADCCON = 0x20;
// power-on the ADC
delay(2000);
ADCCP = 0x10;
// Select Temperature
Sensor as an // input to the ADC
REFCON = 0x01; // connect internal 2.5V
reference // to Vref pin
ADCCON = 0xE4; // continuous conversion
while(1)
{
while (!ADCSTA){};
// wait for end of conversion
b = (ADCDAT >> 16);
// To calculate temperature in 掳C, use
the formula:
a = 0x525 - b;
// ((Temperature = 0x525 - Sensor
Voltage) / 1.3)
a /= 1.3;
b = floor(a);
printf("Temperature: %d
oC\n",b);
}
return 0;
}
BAND GAP REFERENCE
Each ADuC7019/20/21/22/24/25/26/27/28/29 provides an on-
chip band gap reference of 2.5 V, which can be used for the ADC
and DAC. This internal reference also appears on the VREF pin.
When using the internal reference, a 0.47 F capacitor must be
connected from the external VREF pin to AGND to ensure stability
and fast response during ADC conversions. This reference can
also be connected to an external pin (VREF) and used as a refer-
ence for other circuits in the system. An external buffer is required
because of the low drive capability of the VREF output. A program-
mable option also allows an external reference input on the VREF
pin. Note that it is not possible to disable the internal reference.
Therefore, the external reference source must be capable of
overdriving the internal reference source.
Table 29. REFCON Register
Name
Address
Default Value
Access
REFCON
0xFFFF048C
0x00
R/W
The band gap reference interface consists of an 8-bit MMR
REFCON, described in Table 30.
Table 30. REFCON MMR Bit Designations
Bit
Description
7:1
Reserved.
0
Internal reference output enable. Set by user to
connect the internal 2.5 V reference to the VREF pin.
The reference can be used for an external component
but must be buffered. Cleared by user to disconnect
the reference from the VREF pin.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| EVAL-ADUC824QSZ | KIT DEV QUICK START ADUC824 |
| RPS-1K-22-18/2.0-9 | HEAT SHRINK SLEEVE |
| EBM31DCMN | CONN EDGECARD 62POS .156 WW |
| REC5-243.3DRWZ/H/B | CONV DC/DC 5W 9-36VIN +/-3.3V |
| ADR06WARZ-R7 | IC VREF SERIES PREC 3V 8SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| EVAL-ADUC7029QSZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:Silicon Manufacturer:Analog Devices C |
| EVAL-ADUC7032QSPZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:EVAL BD FOR ADUC7032 - Bulk |
| EVAL-ADUC7033QSPZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:QUICK START DEVELOPMENT SYSTEM - Bulk |
| EVAL-ADUC7034QSPZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:EVALUATION BOARD - Boxed Product (Development Kits) |
| EVAL-ADUC7036QSPZ | 鍔熻兘鎻忚堪:BOARD EVAL FOR ADUC7036 RoHS:鏄� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 瑭曚及婕旂ず鏉垮拰濂椾欢 绯诲垪:QuickStart™ PLUS 濂椾欢 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:PSoC® 涓昏鐩殑:闆绘簮绠＄悊锛岀啽绠＄悊 宓屽叆寮�:- 宸茬敤 IC / 闆朵欢:- 涓昏灞€�:- 娆¤灞€�:- 宸蹭緵鐗╁搧:鏉匡紝CD锛岄浕婧� |
鐧�(f膩)甯冪穵鎬ラ噰璩硷紝3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
