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| 型號： | EVAL-ADUC7029QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 54/104頁 |
| 文件大小： | 0K |
| 描述： | EVAL DEV SYSTEM FOR ADUC7029 |
| 設(shè)計(jì)資源： | ADuC70xx Serial Download Protocol ADuC7029 Dev System Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 53 of 104
Table 35. FEECON Register
Name
Address
Default Value
Access
FEECON
0xFFFFF808
0x07
R/W
FEECON is an 8-bit command register. The commands are
described in Table 36.
Table 36. Command Codes in FEECON
Code
Command
Description
0x001
Null
Idle state.
0x011
Single read
Load FEEDAT with the 16-bit data.
Indexed by FEEADR.
0x021
Single write
Write FEEDAT at the address pointed to
by FEEADR. This operation takes 50 s.
0x031
Erase/write
Erase the page indexed by FEEADR and
write FEEDAT at the location pointed by
FEEADR. This operation takes approxi-
mately 24 ms.
0x041
Single verify
Compare the contents of the location
pointed by FEEADR to the data in
FEEDAT. The result of the comparison is
returned in FEESTA, Bit 1.
0x051
Single erase
Erase the page indexed by FEEADR.
0x061
Mass erase
Erase 62 kB of user space. The 2 kB of
kernel are protected. This operation
takes 2.48 sec. To prevent accidental
execution, a command sequence is
required to execute this instruction.
See the Command Sequence for
Executing a Mass Erase section.
0x07
Reserved
Reserved.
0x08
Reserved
Reserved.
0x09
Reserved
Reserved.
0x0A
Reserved
Reserved.
0x0B
Signature
Give a signature of the 64 kB of Flash/EE
in the 24-bit FEESIGN MMR. This
operation takes 32,778 clock cycles.
0x0C
Protect
This command can run only once. The
value of FEEPRO is saved and removed
only with a mass erase (0x06) of the key.
0x0D
Reserved
Reserved.
0x0E
Reserved
Reserved.
0x0F
Ping
No operation; interrupt generated.
1
The FEECON register always reads 0x07 immediately after execution of any
of these commands.
Table 37. FEEDAT Register
Name
Address
Default Value
Access
FEEDAT
0xFFFFF80C
0xXXXX1
R/W
1
X = 0, 1, 2, or 3.
FEEDAT is a 16-bit data register.
Table 38. FEEADR Register
Name
Address
Default Value
Access
FEEADR
0xFFFFF810
0x0000
R/W
FEEADR is another 16-bit address register.
Table 39. FEESIGN Register
Name
Address
Default Value
Access
FEESIGN
0xFFFFF818
0xFFFFFF
R
FEESIGN is a 24-bit code signature.
Table 40. FEEPRO Register
Name
Address
Default Value
Access
FEEPRO
0xFFFFF81C
0x00000000
R/W
FEEPRO MMR provides protection following a subsequent
reset of the MMR. It requires a software key (see Table 42).
Table 41. FEEHIDE Register
Name
Address
Default Value
Access
FEEHIDE
0xFFFFF820
0xFFFFFFFF
R/W
FEEHIDE MMR provides immediate protection. It does not
require any software key. Note that the protection settings in
FEEHIDE are cleared by a reset (see Table 42).
Table 42. FEEPRO and FEEHIDE MMR Bit Designations
Bit
Description
31
Read protection. Cleared by user to protect all code.
Set by user to allow reading the code.
30:0
Write protection for Page 123 to Page 120, Page 119
to Page 116, and Page 0 to Page 3. Cleared by user to
protect the pages from writing. Set by user to allow
writing the pages.
Command Sequence for Executing a Mass Erase
FEEDAT=0x3CFF;
FEEADR = 0xFFC3;
FEEMOD= FEEMOD|0x8;
//Erase key enable
FEECON=0x06;
//Mass erase command
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| EVAL-ADUC7036QSPZ | 功能描述:BOARD EVAL FOR ADUC7036 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:QuickStart™ PLUS 套件 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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