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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | EVAL-ADUC7029QSZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 25/104闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | EVAL DEV SYSTEM FOR ADUC7029 |
| 瑷�(sh猫)瑷�(j矛)璩囨簮锛� | ADuC70xx Serial Download Protocol ADuC7029 Dev System Schematic |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | * |
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Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 27 of 104
Pin No.
Mnemonic
Description
37
P3.6/PWMTRIP/PLAI[14]
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array Input
Element 14.
38
P3.7/PWMSYNC/PLAI[15]
General-Purpose Input and Output Port 3.7/PWM Synchronization Input and Output/
Programmable Logic Array Input Element 15.
39
P1.7/SPM7/PLAO[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
40
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
41
IOGND
Ground for GPIO (see Table 78). Typically connected to DGND.
42
IOVDD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
43
P4.0/PLAO[8]
General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8.
44
P4.1/PLAO[9]
General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9.
45
P1.5/SPM5/PLAI[5]/IRQ3
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
46
P1.4/SPM4/PLAI[4]/IRQ2
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
47
P1.3/SPM3/PLAI[3]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
48
P1.2/SPM2/PLAI[2]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
49
P1.1/SPM1/PLAI[1]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic
Array Input Element 1.
50
P1.0/T1/SPM0/PLAI[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
51
P4.2/PLAO[10]
General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10.
52
P4.3/PLAO[11]
General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11.
53
P4.4/PLAO[12]
General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12.
54
P4.5/PLAO[13]
General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13.
55
VREF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 F capacitor when using the
internal reference.
56
DACREF
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
57
DACGND
Ground for the DAC. Typically connected to AGND.
58
AGND
Analog Ground. Ground reference point for the analog circuitry.
59
AVDD
3.3 V Analog Power.
60
DACVDD
3.3 V Power Supply for the DACs. Must be connected to AVDD.
61
ADC0
Single-Ended or Differential Analog Input 0.
62
ADC1
Single-Ended or Differential Analog Input 1.
63
ADC2/CMP0
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
64
ADC3/CMP1
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
0
EP
Exposed Pad. The pin configuration for the ADuC7024/ADuC7025 LFCSP_VQ has an exposed pad
that must be soldered for mechanical purposes and left unconnected.
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