
Power
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
1-3
1.1  Power
1.2  Ground
1.3  Clock
Table 1-2.     
Power Inputs
Power Name
Description
V
CCQL
Quiet Core (Low) Power
—An isolated power for the core processing and clock logic. This input must be isolated 
externally from all other chip power inputs. 
V
CCQH
Quiet External (High) Power
—A quiet power source for I/O lines. This input must be tied externally to all other chip 
power inputs, except V
CCQL
. 
Address Bus Power
—An isolated power for sections of the address bus I/O drivers. This input must be tied externally 
to all other chip power inputs, except V
CCQL
. 
Data Bus Power
—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all 
other chip power inputs, except V
CCQL
. 
Bus Control Power
—An isolated power for the bus control I/O drivers. This input must be tied externally to all other 
chip power inputs
, 
except V
CCQL
. 
Host Power
—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power 
inputs
, 
except
V
CCQL
. 
ESSI, SCI, and Timer Power
—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied 
externally to all other chip power inputs, except V
CCQL
. 
Note:
 The user must provide adequate external decoupling capacitors for all power connections.
V
CCA
V
CCD
V
CCC
V
CCH
V
CCS
Table 1-3.     
Grounds
Name
Description
GND 
Ground
—Connected to an internal device ground plane.
Note:
 The user must provide adequate external decoupling capacitors for all GND connections.
Table 1-4.     
Clock Signals
Signal Name
Type
State During 
Reset
Signal Description
EXTAL
Input
Input
External Clock/Crystal Input
—Interfaces the internal crystal oscillator input 
to an external crystal or an external clock.
XTAL
Output
Chip-driven
Crystal Output
—Connects the internal crystal oscillator output to an external 
crystal. If an external clock is used, leave XTAL unconnected.