- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377000 > DSP56321 (飛思卡爾半導(dǎo)體(中國(guó))有限公司) 24-Bit Digital Signal Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP56321 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 24-Bit Digital Signal Processor |
| 中文描述： | 24位數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 8/84頁(yè) |
| 文件大?。?/td> | 898K |
| 代理商： | DSP56321 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)
DSP56321 Technical Data, Rev. 11
1-2
Freescale Semiconductor
Signals/Connections
Figure 1-1.
Signals Identified by Functional Group
Notes:
1.
The HI08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (DS), and single or
double host request (HR) configurations. Since each of these modes is configured independently, any combination of
these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).
Signals with dual designations (for example, HAS/HAS) have configurable polarity.
The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
TIO[0–2] can be configured as GPIO signals.
2.
3.
DSP56321
24
18
External
Address Bus
External
Data Bus
External
Bus
Control
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0)
2
Timers
3
OnCE/
JTAG Port
Power Inputs:
Core Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
A[0–17]
D[0–23]
AA[0–3]
RD
WR
TA
BR
BG
BB
TCK
TDI
TDO
TMS
TRST
DE
V
CCQL
V
CCQH
V
CCA
V
CCD
V
CCC
V
CCH
V
CCS
5
3
Serial
Communications
Interface (SCI) Port
2
4
2
2
Grounds:
Ground plane
GND
66
Interrupt/
Mode Control
MODA
MODB
MODC
MODD
RESET
PINIT
Host
Interface
(HI08) Port
1
Non-Multiplexed
Bus
H[0–7]
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
RXD
TXD
SCLK
SC0[0–2]
SCK0
SRD0
STD0
TIO0
TIO1
TIO2
8
3
3
EXTAL
XTAL
Clock
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1)
2
SC1[0–2]
SCK1
SRD1
STD1
3
Multiplexed
Bus
HAD[0–7]
HAS/HAS
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
Port E GPIO
PE0
PE1
PE2
Port C GPIO
PC[0–2]
PC3
PC4
PC5
Port D GPIO
PD[0–2]
PD3
PD4
PD5
Timer GPIO
TIO0
TIO1
TIO2
Port A
4
IRQA
IRQB
IRQC
IRQD
RESET
NMI
During Reset
After Reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56321VF200 | 24-Bit Digital Signal Processor |
| DSP56321VF220 | 24-Bit Digital Signal Processor |
| DSP56321VF240 | 24-Bit Digital Signal Processor |
| DSP56321VF275 | 24-Bit Digital Signal Processor |
| DSP56321VL200 | 24-Bit Digital Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56321EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 DSP56321EVM RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| DSP56321EVMUM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56321 EVM User＇s Manual |
| DSP56321FC200 | 制造商:Freescale Semiconductor 功能描述:HIP7 56321 200MHZ DSP - Trays |
| DSP56321FC220 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DSP56321RMAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56321 Reference Manual Addendum |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。