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參數(shù)資料
| 型號(hào)： | DSP56321 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 24-Bit Digital Signal Processor |
| 中文描述： | 24位數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 34/84頁(yè) |
| 文件大?。?/td> | 898K |
| 代理商： | DSP56321 |
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DSP56321 Technical Data, Rev. 11
2-14
Freescale Semiconductor
Specifications
The asynchronous bus arbitration is enabled by internal synchronization circuits on
BG
and
BB
inputs. These
synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this
delay, a DSP56300 part may assume mastership and assert
BB
, for some time after
BG
is deasserted. This is the
reason for timing 250.
Once
BB
is asserted, there is a synchronization delay from
BB
assertion to the time this assertion is exposed to other
DSP56300 components that are potential masters on the same bus. If
BG
input is asserted before that time, and
BG
is asserted and
BB
is deasserted, another DSP56300 component may assume mastership at the same time.
Therefore, some non-overlap period between one
BG
input active to another
BG
input active is required. Timing 251
ensures that overlaps are avoided.
2.4.6
Host Interface Timing
Figure 2-12.
Asynchronous Bus Arbitration Timing
Table 2-10.
Host Interface Timings
1,2,12
No.
Characteristic
10
Expression
200 MHz
220 MHz
240 MHz
275 MHz
Uni
t
Min
Max
Min
Max
Min
Max
Min
Max
317
Read data strobe assertion width
5
HACK assertion width
T
C
+ 4.95
9.95
—
9.05
—
8.3
—
7.77
—
ns
318
Read data strobe deassertion width
5
HACK deassertion width
4.95
—
4.5
—
4.13
—
4.0
—
ns
319
Read data strobe deassertion width
5
after
“Last Data Register” reads
8,11
, or between two
consecutive CVR, ICR, or ISR reads
3
HACK deassertion width after “Last Data
Register” reads
8,11
2.5
×
T
C
+ 3.3
15.8
—
14.7
—
13.7
—
12.39
—
ns
320
Write data strobe assertion width
6
6.6
—
6.0
—
5.5
—
5.1
—
ns
321
Write data strobe deassertion width
8
HACK write deassertion width
after ICR, CVR and “Last Data Register”
writes
after IVR writes, or
after TXH:TXM:TXL writes (with HLEND=
0), or
after TXL:TXM:TXH writes (with HLEND =
1)
2.5
×
T
C
+ 3.3
15.8
8.25
—
—
14.7
7.5
—
—
13.7
6.88
—
—
12.39
6.28
—
—
ns
ns
322
HAS assertion width
4.95
—
4.5
—
4.13
—
4.0
—
ns
BG1
BB
251
BG2
250
250+251
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56321VF200 | 24-Bit Digital Signal Processor |
| DSP56321VF220 | 24-Bit Digital Signal Processor |
| DSP56321VF240 | 24-Bit Digital Signal Processor |
| DSP56321VF275 | 24-Bit Digital Signal Processor |
| DSP56321VL200 | 24-Bit Digital Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56321EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 DSP56321EVM RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| DSP56321EVMUM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56321 EVM User＇s Manual |
| DSP56321FC200 | 制造商:Freescale Semiconductor 功能描述:HIP7 56321 200MHZ DSP - Trays |
| DSP56321FC220 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DSP56321RMAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56321 Reference Manual Addendum |
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