參數(shù)資料
型號(hào)： DSP56321
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Digital Signal Processor
中文描述： 24位數(shù)字信號(hào)處理器
文件頁數(shù)： 7/84頁
文件大小： 898K
代理商： DSP56321
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
1-1
Signals/Connections
1
The DSP56321 input and output signals are organized into functional groups as shown in
Table 1-1
.
Figure 1-1
diagrams the DSP56321 signals by functional group. The remainder of this chapter describes the signal pins in
each functional group.
Note:
This chapter refers to a number of configuration registers used to select individual multiplexed signal
functionality. See the
DSP56321 Reference Manual
for details on these configuration registers.
Table 1-1.
DSP56321 Functional Signal Groupings
Functional Group
Number of
Signals
Power (V
CC
)
20
Ground (GND)
66
Clock
2
Address bus
Port A
1
18
Data bus
24
Bus control
10
Interrupt and mode control
6
Host interface (HI08)
Port B
2
16
Enhanced synchronous serial interface (ESSI)
Ports C and D
3
12
Serial communication interface (SCI)
Port E
4
3
Timer
3
OnCE/JTAG Port
6
Notes:
1.
2.
3.
4.
5.
Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.
Port B signals are the HI08 port signals multiplexed with the GPIO signals.
Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
Port E signals are the SCI port signals multiplexed with the GPIO signals.
Eight signal lines are not connected internally. These are designated as no connect (NC) in the package description (see
Chapter 3
). There are also two reserved lines.
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