參數(shù)資料
型號(hào)： DSP56321
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Digital Signal Processor
中文描述： 24位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 3/84頁(yè)
文件大小： 898K
代理商： DSP56321
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
iii
Features
Table 1
lists the features of the DSP56321 device.
Table 1.
DSP56321 Features
Feature
Description
High-Performance
DSP56300 Core
275 million multiply-accumulates per second (MMACS) (550 MMACS using the EFCOP in filtering
applications) with a 275 MHz clock at 1.6 V core and 3.3 V I/O
Object code compatible with the DSP56000 core with highly parallel instruction set
Data arithmetic logic unit (Data ALU) with fully pipelined 24
×
24-bit parallel Multiplier-Accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
Program control unit (PCU) with position independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG)
test access port (TAP)
Internal 24
×
24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
Operation at the same frequency as the core (up to 275 MHz)
Support for a variety of filter modes, some of which are optimized for cellular base station applications:
Real finite impulse response (FIR) with real taps
Complex FIR with complex taps
Complex FIR generating pure real or pure imaginary outputs alternately
A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
Direct form 2 (DFII) IIR filter
Four scaling factors (1, 4, 8, 16) for IIR output
Adaptive FIR filter with true least mean square (LMS) coefficient updates
Adaptive FIR filter with delayed LMS coefficient updates
Enhanced Filter
Coprocessor (EFCOP)
Internal Peripherals
Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
Serial communications interface (SCI) with baud rate generator
Triple timer module
Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
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