參數(shù)資料
型號(hào)： DSP56321
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Digital Signal Processor
中文描述： 24位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 4/84頁(yè)
文件大?。?/td> 898K
代理商： DSP56321
DSP56321 Technical Data, Rev. 11
iv
Freescale Semiconductor
Target Applications
DSP56321 applications require high performance, low power, small packaging, and a large amount of internal
memory. The EFCOP can accelerate general filtering applications. Examples include:
Wireless and wireline infrastructure applications
Multi-channel wireless local loop systems
Security encryption systems
Home entertainment systems
DSP resource boards
High-speed modem banks
IP telephony
Internal Memories
192
×
24-bit bootstrap ROM
192 K
×
24-bit RAM total
Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
External Memory
Expansion
Data memory expansion to two 256 K
×
24-bit word memory spaces using the standard external address
lines
Program memory expansion to one 256 K
×
24-bit words memory space using the standard external
address lines
External memory expansion port
Chip select logic for glueless interface to static random access memory (SRAMs)
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.
Power Dissipation
Packaging
Table 1.
DSP56321 Features (Continued)
Feature
Description
:
Program RAM
Size
32 K
×
24-bit
31 K
×
24-bit
40 K
×
24-bit
39 K
×
24-bit
48 K
×
24-bit
47 K
×
24-bit
64 K
×
24-bit
63 K
×
24-bit
72 K
×
24-bit
71 K
×
24-bit
80 K
×
24-bit
79 K
×
24-bit
96 K
×
24-bit
95 K
×
24-bit
112 K
×
24-bit
111 K
×
24-bit
*Includes 12 K
×
24-bit shared memory (that is, 24 K total memory shared by the core and the EFCOP)
Instruction
Cache Size
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
X Data RAM
Size*
80 K
×
24-bit
80 K
×
24-bit
76 K
×
24-bit
76 K
×
24-bit
72 K
×
24-bit
72 K
×
24-bit
64 K
×
24-bit
64 K
×
24-bit
60 K
×
24-bit
60 K
×
24-bit
56 K
×
24-bit
56 K
×
24-bit
48 K
×
24-bit
48 K
×
24-bit
40 K
×
24-bit
40 K
×
24-bit
Y Data RAM
Size*
80 K
×
24-bit
80 K
×
24-bit
76 K
×
24-bit
76 K
×
24-bit
72 K
×
24-bit
72 K
×
24-bit
64 K
×
24-bit
64 K
×
24-bit
60 K
×
24-bit
60 K
×
24-bit
56 K
×
24-bit
56 K
×
24-bit
48 K
×
24-bit
48 K
×
24-bit
40 K
×
24-bit
40 K
×
24-bit
Instruction
Cache
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
MSW2
MSW1
MSW0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
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