參數(shù)資料
型號(hào)： DSP1620
英文描述： TVS 400W 6.0V BIDIRECT SMA
中文描述： 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說明
文件頁數(shù)： 88/114頁
文件大小： 804K
代理商： DSP1620
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
86
10 Timing Characteristics for 2.7 V Operation
The following timing characteristics and requirements are preliminary information and are subject to change. Timing
characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions
imposed on the user for proper operation of the device. All timing data is valid for the following conditions:
T
A
= –40
°
C to +85
°
C (See Section 8.3.)
V
DD
= 3 V
±
10%, V
SS
= 0 V (See Section 8.3.)
Capacitance load on outputs (C
L
) = 50 pF, except for CKO, where C
L
= 20 pF
Output characteristics can be derated as a function of load capacitance (C
L
).
All outputs: 0.03 ns/pF
≤
dt/dC
L
≤
0.07 ns/pF for 10
≤
C
L
≤
100 pF
at V
IH
for rising edge and at V
IL
for falling edge
For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF
x 0.06 ns/pF = 1.2 ns
less
than the specified rise time or delay that includes a rise time.
Test conditions for inputs:
I
Rise and fall times of 4 ns or less
Timing reference levels for delays = V
IH
, V
IL
I
Test conditions for outputs (unless noted otherwise):
I
C
LOAD
= 50 pF; except for CKO, where C
LOAD
= 20 pF
Timing reference levels for delays = V
IH
, V
IL
3-state delays measured to the high-impedance state of the output driver
I
I
For the timing diagrams, see Table 62 for input clock requirements.
Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.
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