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參數(shù)資料
| 型號(hào)： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 30/114頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
28
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
Generating polynomials, G(0), . . . , G(5), up to six-delays corresponding to a constraint length of seven, may take
part in computing the estimated received signals, E(0, k), . . . , E(5, k), within the ECCP associated with all possible
state transitions, k = 0, 1, 2C – 1.
Six 8-bit soft symbols, S(0), . . . , S(5), are loaded into the ECCP. The incremental branch metrics associated with
all 2C state transitions are calculated as indicated in Table 10:
The received 8-bit signals S(5) through S(0) are stored in the S5H5 through S0H0 registers. The generating poly-
nomials G(1) and G(0) are stored in the upper and lower bytes of the ZIG10 register, respectively. The generating
polynomials G(3) and G(2) are stored in the upper and lower bytes of the ZQG32 register, respectively. The gener-
ating polynomials G(5) and G(4) are stored in the upper and lower bytes of the G54 register, respectively.
Update Unit:
The add-compare-select operation of the Viterbi algorithm is performed in this unit. At every time in-
stant, there are 2C state transitions of which 2C – 1 state transitions survive. The update unit selects and updates
2C – 1 surviving sequences in the traceback RAM that consists of the 4th bank of the internal RAM, RAM4. The
accumulated cost of the path p at the Jth instant, ACC(J, p), is the sum of the incremental branch metrics belonging
to the path p up to the time instant J:
ACC(J, p) =
∑
BM(j, p), j = 1, . . . , J
The update unit computes and stores full precision 24-bit resolution path metrics of the bit sequence. To assist the
detection of a near overflow in the accumulated path cost, an internal vectored interrupt, EOVF, is provided.
Traceback Unit:
The traceback unit selects a path with the smallest path metric among 2C – 1 survivor paths at
every instant. The last signal of the path corresponding to the maximum likelihood sequence is delivered to the
decoder output. The depth of this last signal is programmable at the symbol rate. The traceback decoding starts
from the minimum cost index associated with the state with the minimum cost, min {Acc(j, p1), . . . , Acc(j, p2C – 1)}.
If the end state is known, the traceback decoding may be forced in the direction of the right path by writing the de-
sired end state into the minimum cost index register, MIDX.
Interrupts and Flags:
The ECCP interrupts the DSP1600 core when the ECCP has completed an instruction,
EREADY, or when an overflow in the accumulated cost is imminent, EOVF. Also, an EBUSY flag is provided to the
core to indicate when the ECCP is in operation.
Traceback RAM:
The fourth 1 Kword bank of dual-port RAM is shared between the DSP1600 core and the ECCP.
RAM4, located in the Y memory space in the address range 0x0C00 to 0x0FFF, is used by the ECCP for storing
traceback information. When the ECCP is active, i.e., the EBUSY flag is asserted, the DSP core cannot access this
traceback RAM.
Table 10. Incremental Branch Metrics
Distance Measure
Euclidean
Euclidean
Manhattan
Manhattan
Manhattan
Manhattan
Code Rate
1/1
1/2
1/1
1/2
1/3 or 1/4
1/5 or 1/6
16-bit Incremental Branch Metric
(S(0) – E(0))
2
[
∑
(S(
i
) – E(
i
))
2
] >> 1,
i
= 0, 1
[S(
i
) – E(
i
)] << 8,
i
= 0
[(S(
i
) – E(
i
))] << 7,
i
= 0, 1
[(S(
i
) – E(
i
))] << 6,
i
= 0, 1, 2, or 3
[(S(
i
) – E(
i
))] << 5,
i
= 0, 1, . . . , 4 or 5
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