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參數(shù)資料
| 型號(hào)： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說明 |
| 文件頁(yè)數(shù)： | 13/114頁(yè) |
| 文件大小： | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
11
4 Hardware Architecture
(continued)
Table 2. DSP1628 Block Diagram Legend
Symbol
aa<0—1>
ar<0—3>
BIO
BMU
BREAKPOINT
BYPASS
cbit
Dual-Port RAM
ECCP
ear
edr
eir
EMUX
HDS
ID
IDB
ioc
JCON
jtag
pdx0(in)
pdx0(out)
PHIF
phifc
pllc
powerc
PSTAT
saddx
saddx2
sbit
sdx(in)
sdx2(in)
sdx(out)
sdx2(out)
SIO
SIO2
sioc
sioc2
srta
srta2
tdms
tdms2
TIMER
timer0
timerc
TRACE
XAB
XDB
YAB
YDB
Name
Alternate Accumulators.
Auxiliary BMU Registers.
Bit Input/Output Unit.
Bit Manipulation Unit.
Four Instruction Breakpoint Registers.
JTAG Bypass Register.
Control Register for BIO.
Internal RAM (16 Kwords for DSP1628x16, 8 Kwords for DSP1628x08).
Error Correction Coprocessor.
Error Correction Coprocessor Address Register.
Error Correction Coprocessor Data Register.
Error Correction Coprocessor Instruction Register.
External Memory Multiplexer.
Hardware Development System.
JTAG Device Identification Register.
Internal Data Bus.
I/O Configuration Register.
JTAG Configuration Registers.
16-bit Serial/Parallel Register.
Parallel Data Transmit Input Register 0.
Parallel Data Transmit Output Register 0.
Parallel Host Interface.
Parallel Host Interface Control Register.
Phase-Locked Loop Control Register.
Power Control Register.
Parallel Host Interface Status Register.
Multiprocessor Protocol Register.
Multiprocessor Protocol Register for SIO2.
Status Register for BIO.
Serial Data Transmit Input Register.
Serial Data Transmit Input Register for SIO2.
Serial Data Transmit Output Register.
Serial Data Transmit Output Register for SIO2.
Serial Input/Output Unit.
Serial Input/Output Unit #2.
Serial I/O Control Register.
Serial I/O Control Register for SIO2.
Serial Receive/Transmit Address Register.
Serial Receive/Transmit Address Register for SIO2.
Serial I/O Time-division Multiplex Signal Control Register.
Serial I/O Time-division Multiplex Signal Control Register for SIO2.
Programmable Timer.
Timer Running Count Register.
Timer Control Register.
Program Discontinuity Trace Buffer.
Program Memory Address Bus.
Program Memory Data Bus.
Data Memory Address Bus.
Data Memory Data Bus.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP16210 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP16210 Digital Signal Processor |
| DSP1627 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1627 Digital Signal Processor |
| DSP1627F32K10IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
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