- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄377000 > DSP1620 TVS 400W 6.0V BIDIRECT SMA PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 78/114頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1620 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)當(dāng)前第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
76
Lucent Technologies Inc.
6 Signal Descriptions
(continued)
6.4 Parallel Host Interface or Serial
Interface #2 and Control I/O Interface
This interface pin multiplexes a parallel host interface
with a second serial I/O interface and a 4-bit I/O inter-
face. The interface selection is made by writing the
ESIO2 bit in the
ioc
register (see Table 42 and
Section 4.1). The functions and signals for the second
SIO correspond exactly with those in SIO #1. Therefore,
the pin descriptions below discuss only PHIF and BIO
pin functionality.
PB[7:0]
Parallel I/O Data Bus:
This 8-bit bidirectional bus is
used to input data to, or output data from, the PHIF.
Note that PB[3:0] are pin multiplexed with SIO2 func-
tionality, and PB[7:4] are pin multiplexed with BIO unit
pins IOBIT[3:0] (see Section 4.1).
PCSN
Peripheral Chip Select Not:
Negative assertion.
PCSN is an input. While PCSN is low, the data strobes
PIDS and PODS are enabled. While PCSN is high, the
DSP1628 ignores any activity on PIDS and PODS.
PBSEL
Peripheral Byte Select:
An input pin, configurable in
software. Selects the high or low byte of
pdx0
available
for host accesses.
PSTAT
Peripheral Status Select:
PSTAT is an input. When a
logic 0, the PHIF will output the
pdx0
[out] register on
the PB bus. When a logic 1, the PHIF will output the
contents of the PSTAT register on PB[7:0].
PIDS
Parallel Input Data Strobe:
An input pin, software con-
figurable to support both Inteland Motorolaprotocols.
In Intelmode: Negative assertion. PIDS is pulled low by
an external device to indicate that data is available on
the PB bus. The DSP latches data on the PB bus on the
rising edge (low-to-high transition) of PIDS or PCSN,
whichever comes first.
In Motorolamode: PIDS/PRWN functions as a read/
write strobe. The external device sets PIDS/PRWN to a
logic 0 to indicate that data is available on the PB bus
(write operation by the external device). A logic 1 on
PIDS/PRWN indicates an external read operation by
the external device.
PODS
Parallel Output Data Strobe:
An input pin, software
configurable to support both Inteland Motorolaproto-
cols.
In Intelmode: Negative assertion. When PODS is
pulled low by an external device, the DSP1628 places
the contents of the parallel output register,
pdx0
, onto
the PB bus.
In Motorolamode: Software-configurable assertion
level. The external device uses PODS/PDS as its data
strobe for both read and write operations.
PIBF
Parallel Input Buffer Full:
An output pin with positive
assertion; configurable in software. This flag is cleared
after reset, indicating an empty input buffer
pdx0
[in].
PIBF is set immediately after the rising edge of PIDS or
PCSN, indicating that data has been latched into the
pdx0
[in] register. When the DSP1628 reads the con-
tents of this register, emptying the buffer, the flag is
cleared.
Configured in software, PIBF may become the logical
OR of the PIBF and POBE flags.
POBE
Parallel Output Buffer Empty:
An output pin with pos-
itive assertion; configurable in software. This flag is set
after reset, indicating an empty output buffer
pdx0
[out].
POBE is set immediately after the rising edge of PODS
or PCSN, indicating that the data in
pdx0
[out] has been
driven onto the PB bus. When the DSP1628 writes to
pdx0
[out], filling the buffer, this flag is cleared.
6.5 Control I/O Interface
This interface is used for status and control operations
provided by the bit I/O unit of the DSP1628. It is pin mul-
tiplexed with the PHIF and VEC[3:0] pins (see Section
4.1). Setting the ESIO2 and EBIOH bits in the
ioc
reg-
ister provides a full 8-bit BIO interface at the associated
pins.
IOBIT[7:0]
I/O Bits [7:0]:
Each of these bits can
be independently
configured as either an input or an output. As outputs,
they can be independently set, toggled, or cleared. As
inputs, they can be tested independently or in combina-
tions for various data patterns.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP1628 | TVS 400W 60V BIDIRECT SMA |
| DSP16210 | TVS 400W 6.5V UNIDIRECT SMA |
| DSP1627 | TVS 400W 6.5V BIDIRECT SMA |
| DSP1629 | TVS 400W 64V UNIDIRECT SMA |
| DSP16410C | TVS 400W 7.0V UNIDIRECT SMA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP16210 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP16210 Digital Signal Processor |
| DSP1627 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1627 Digital Signal Processor |
| DSP1627F32K10IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。