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參數(shù)資料
| 型號： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數(shù)： | 36/114頁 |
| 文件大小： | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
34
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
4.12 JTAG Test Port
The DSP1628 uses a JTAG/IEEE1149.1 standard five-
wire test port (TDI, TDO, TCK, TMS, TRST) for self-test
and hardware emulation. An instruction register, a
boundary-scan register, a bypass register, and a device
identification register have been implemented. The de-
vice identification register coding for the DSP1628 is
shown in Table 41. The instruction register (IR) is 4 bits
long. The instruction for accessing the device ID is 0xE
(1110). The behavior of the instruction register is sum-
marized in Table 14. Cell 0 is the LSB (closest to TDO).
The first line shows the cells in the IR that capture from
a parallel input in the capture-IR controller state. The
second line shows the cells that always load a logic 1 in
the capture-IR controller state. The third line shows the
cells that always load a logic 0 in the capture-IR control-
ler state. Cell 3 (MSB of IR) is tied to status signal PINT,
and cell 2 is tied to status signal JINT. The state of these
signals can therefore be captured during capture-IR and
shifted out during SHIFT-IR controller states.
Boundary-Scan Register
All of the chip's inputs and outputs are incorporated in a
JTAG scan path shown in Table 15. The types of
boundary-scan cells are as follows:
I
I = input cell
I
O = 3-state output cell
I
B = bidirectional (I/O) cell
I
OE = 3-state control cell
I
DC = bidirectional control cell
Table 14. JTAG Instruction Register
IR Cell #:
parallel input
always logic 1
always logic 0
3
Y
N
N
2
Y
N
N
1
N
N
Y
0
N
Y
N
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| DSP1627F32K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC |
| DSP1627F32K11I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
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