參數(shù)資料
型號： DSP1620
英文描述： TVS 400W 6.0V BIDIRECT SMA
中文描述： 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明
文件頁數(shù)： 52/114頁
文件大?。?/td> 804K
代理商： DSP1620
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
50
Lucent Technologies Inc.
5 Software Architecture
(continued)
Conditional Mnemonics (Flags)
Table 21 lists mnemonics used in conditional execution of special function and control instructions.
*
Result is not representable in the 36-bit accumulators (36-bit overflow).
Bits 35—31 are not the same (32-bit overflow).
Notes:
Testing the state of the counters (
c0
or
c1
) automatically increments the counter by one.
The heads or tails condition is determined by a randomly set or cleared bit, respectively. The bit is randomly set with a probability of 0.5. A random
rounding function can be implemented with either heads or tails. The random bit is generated by a ten-stage pseudorandom sequence generator
(PSG) that is updated after either a heads or tails test. The pseudorandom sequence may be reset by writing any value to the
pi
register, except
during an interrupt service routine (ISR). While in an ISR, writing to the
pi
register updates the register and does not reset the PSG. If not in an
ISR, writing to the
pi
register resets the PSG. (The
pi
register is updated, but will be written with the contents of the PC on the next instruction.)
Interrupts must be disabled when writing to the pi register.
If an interrupt is taken after the
pi
write, but before
pi
is updated with the PC
value, the
ireturn
instruction will not return to the correct location. If the RAND bit in the
auc
register is set, however, writing the
pi
register never
resets the PSG.
Table 21. DSP1628 Conditional Mnemonics
Test
pl
eq
gt
lvs
mvs
c0ge
c1ge
heads
Meaning
Test
mi
ne
le
lvc
mvc
c0lt
c1lt
tails
Meaning
Result is nonnegative (sign bit is bit 35).
≥
0
Result is equal to 0. = 0
Result is greater than 0. > 0
Logical overflow set.
*
Mathematical overflow set.
Counter 0 greater than or equal to 0.
Counter 1 greater than or equal to 0.
Pseudorandom sequence bit set.
The condition is always satisfied in an if in-
struction.
All True, all BIO input bits tested compared
successfully.
Some True, some BIO input bits tested com-
pared successfully.
Odd Parity, from BMU operation.
Minus 1, result of BMU operation.
Not PINT, used by hardware development
system.
Result is negative. < 0
Result is not equal to 0.
≠
0
Result is less than or equal to 0.
≤
0
Logical overflow clear.
Mathematical overflow clear.
Counter 0 less than 0.
Counter 1 less than 0.
Pseudorandom sequence bit clear.
The condition is never satisfied in an if in-
struction.
All False, no BIO input bits tested compared
successfully.
Some False, some BIO input bits tested did
not compare successfully.
Even Parity, from BMU operation.
Not Minus 1, result of BMU operation.
Not JINT, used by hardware development
system.
ECCP Busy, indicates error correction copro-
cessor activity.
true
false
allt
allf
somet
somef
oddp
mns1
evenp
nmns1
npint
njint
lock
The PLL has achieved lock and is stable.
ebusy
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