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| 型號： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數(shù)： | 24/114頁 |
| 文件大小： | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
22
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
4.6 Bit Manipulation Unit (BMU)
The BMU interfaces directly to the main accumulators in
the DAU providing the following features:
I
Barrel shifting—logical and arithmetic, left and right
shift
I
Normalization and extraction of exponent
I
Bit-field extraction and insertion
These features increase the efficiency of the DSP in ap-
plications such as control or data encoding and decod-
ing. For example, data packing and unpacking, in which
short data words are packed into one 16-bit word for
more efficient memory storage, is very easy.
In addition, the BMU provides two auxiliary accumula-
tors,
aa0
and
aa1
. In one instruction cycle, 36-bit data
can be shuffled, or swapped, between one of the main
accumulators and one of the alternate accumulators.
The
ar<0—3>
registers are 16-bit registers that control
the operations of the BMU. They store a value that de-
termines the amount of shift or the width and offset
fields for bit extraction or insertion. Certain operations in
the BMU set flags in the DAU
psw
register and the
alf
register (see Table 30, Processor Status Word (
psw
)
Register, and Table 39,
alf
Register). The
ar<0—3>
registers can also be used as general-purpose regis-
ters.
The BMU instructions are detailed in Section 5.1. For a
thorough description of the BMU, see the DSP1611/17/
18/27 Digital Signal Processor Information Manual
4.7 Serial I/O Units (SIOs)
The serial I/O ports on the DSP1628 device provide a
serial interface to many codecs and signal processors
with little, if any, external hardware required. Each high-
speed, double-buffered port (
sdx
and
sdx2
) supports
back-to-back transmissions of data. SIO and SIO2 are
identical. The output buffer empty (OBE and OBE2) and
input buffer full (IBF and IBF2) flags facilitate the read-
ing and/or writing of each serial I/O port by program-
or interrupt-driven I/O. There are four selectable active
clock speeds.
A bit-reversal mode provides compatibility with either
the most significant bit (MSB) first or least significant bit
(LSB) first serial I/O formats (see Table 26, Serial I/O
Control Registers (
sioc
and
sioc2
)). A multiprocessor
I/O configuration is supported. This feature allows up to
eight DSP161X devices to be connected together on an
SIO port without requiring external glue logic.
The serial data may be internally looped back by setting
the SIO loopback control bit, SIOLBC, of the
ioc
regis-
ter. SIOLBC affects both the SIO and SIO2. The data
output signals are wrapped around internally from the
output to the input (DO1 to DI1 and DO2 to DI2). To ex-
ercise loopback, the SIO clocks (ICK1, ICK2, OCK1,
and OCK2) should either all be in the active mode,
16-bit condition, or each pair should be driven from one
external source in passive mode. Similarly, pins ILD1
(ILD2) and OLD1 (OLD2) must both be in active mode
or tied together and driven from one external frame
clock in passive mode. During loopback, DO1, DO2,
DI1, DI2, ICK1, ICK2, OCK1, OCK2, ILD1, ILD2, OLD1,
OLD2, SADD1, SADD2, SYNC1, SYNC2, DOEN1, and
DOEN2 are 3-stated.
Setting DODLY = 1 (
sioc
and
sioc2
) delays DO by one
phase of OCK so that DO changes on the falling edge
of OCK instead of the rising edge (DODLY = 0). This re-
duces the time available for DO to drive DI and to be val-
id for the rising edge of ICK, but increases the hold time
on DO by half a cycle on OCK.
Programmable Modes
Programmable modes of operation for the SIO and
SIO2 are controlled by the serial I/O control registers
(
sioc
and
sioc2
). These registers, shown in Table 26,
are used to set the ports into various configurations.
Both input and output operations can be independently
configured as either active or passive. When active, the
DSP1628 generates load and clock signals. When pas-
sive, load and clock signal pins are inputs.
Since input and output can be independently config-
ured, each SIO has four different modes of operation.
Each of the
sioc
registers is also used to select the fre-
quency of active clocks for that SIO. Finally, these reg-
isters are used to configure the serial I/O data formats.
The data can be 8 or 16 bits long, and can also be input/
output MSB first or LSB first. Input and output data for-
mats can be independently configured.
Multiprocessor Mode
The multiprocessor mode allows up to eight devices
that support multiprocessor mode (codecs or DSP16XX
devices) to be connected together to provide data trans-
mission among any of the multiprocessor devices in the
system. Either of the DSP1628’s SIO ports (SIO or
SIO2) may be independently used for the multiproces-
sor mode. The multiprocessor interface is a four-wire in-
terface, consisting of a data channel, an address/
protocol channel, a transmit/receive clock, and a sync
signal (see Figure 6). The DI1 and DO1 pins of all the
DSPs are connected to transmit and receive the data
channel. The SADD1 pins of all the DSPs are connect-
ed to transmit and receive the address/protocol chan-
nel. ICK1 and OCK1 should be tied together and driven
from one source. The SYNC1 pins of all the DSPs are
connected.
In the configuration shown in Figure 6, the master DSP
(DSP0) generates active SYNC1 and OCK1 signals
while the slave DSPs use the SYNC1 and OCK1 signals
in passive mode to synchronize operations. In addition,
all DSPs must have their ILD1 and OLD1 signals in ac-
tive mode.
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