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| 型號： | DSP1620 |
| 英文描述： | TVS 400W 6.0V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數(shù)： | 101/114頁 |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1620 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
99
Lucent Technologies Inc.
10 Timing Characteristics for 2.7 V Operation
(continued)
Figure 24. PHIF MotorolaMode Signaling (Read and Write) Timing Diagram
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also
be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For
example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low after
PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to PCSN
should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
PDS is programmable to be active-high or active-low. It is shown active-low in Figures 24 and 25. POBE and PIBF may be programmed to be
the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Table 88. Timing Requirements for PHIF MotorolaMode Signaling
Abbreviated Reference
Parameter
Min
Max
Unit
t41
PDS
to PCSN Setup (valid to low)
0
—
ns
t42
PCSN to PDS
Hold (high to invalid)
PRWN to PCSN Setup (valid to low)
PCSN to PRWN Hold (high to invalid)
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
PB Write to PCSN Setup (valid to high)
PCSN to PB Write Hold (high to invalid)
0
—
ns
t43
t44
t45*
t46*
t47*
t48*
t51*
t52*
4
0
4
0
6
0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
10
4
Table 89. Timing Characteristics for PHIF MotorolaMode Signaling
Abbreviated Reference
t49*
t50*
t154
Parameter
Min
—
0
—
Max
12
—
8
Unit
ns
ns
ns
PCSN to PB Read (low to valid)
PCSN to PB Read Hold (high to invalid)
PCSN to PB Read 3-state (high to 3-state)
PCSN
PDS
PRWN
PBSEL
PSTAT
PB[7:0]
t41
t42
t43
t44
t45
t46
t47
t48
t52
t51
t50
t154
t49
16-bit READ
16-bit WRITE
t43
t44
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
5-4038 (C).a
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