參數(shù)資料
型號： DSP1620
英文描述： TVS 400W 6.0V BIDIRECT SMA
中文描述： 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明
文件頁數(shù)： 53/114頁
文件大小： 804K
代理商： DSP1620
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
51
5 Software Architecture
(continued)
F3 ALU Instructions
These instructions are implemented in the DSP1600 core. They allow accumulator two-operand operations with ei-
ther another accumulator, the
p
register, or a 16-bit immediate operand (IM16). The result is placed in a destination
accumulator that can be independently specified. All operations are done with the full 36 bits. For the accumulator
with accumulator operations, both inputs are 36 bits. For the accumulator with
p
register operations, the
p
register
is sign-extended into bits 35—32 before the operation. For the accumulator high with immediate operations, the im-
mediate is sign-extended into bits 35—32 and the lower bits 15—0 are filled with zeros, except for the AND opera-
tion, for which they are filled with ones. These conventions allow the user to do operations with 32-bit immediates
by programming two consecutive 16-bit immediate operations. The F3 ALU instructions are shown in Table 22.
Table 22. F3 ALU Instructions
Note:
The F3 ALU instructions that do not have a destination accumulator are used to set flags for conditional
operations, i.e., bit test operations.
If PC points to external memory, add programmed wait-states.
The
h
and
l
are required notation in these instructions.
F4 BMU Instructions
The bit manipulation unit in the DSP1628 provides a set of efficient bit manipulation operations on accumulators. It
contains four auxiliary registers,
ar<0—3>
(
arM
,
M
= 0, 1, 2, 3), two alternate accumulators (
aa0
—
aa1
), which can
be shuffled with the working set, and four flags (oddp, evenp, mns1, and nmns1). The flags are testable by condi-
tional instructions and can be read and written via bits 4—7 of the
alf
register. The BMU also sets the LMI, LEQ,
LLV, and LMV flags in the
psw
register:
LMI = 1 if negative (i.e., bit 35 = 1)
LEQ = 1 if zero (i.e., bits 35—0 are 0)
LLV = 1 if (a) 36-bit overflow, or if (b) illegal shift on field width/offset condition
LMV = 1 if bits 31—35 are not the same (32-bit overflow)
The BMU instructions and cycle times follow. (If PC points to external memory, add programmed wait-states.) All
BMU instructions require 1 word of program memory unless otherwise noted. Please refer to the DSP1611/17/18/
27 Digital Signal Processor Information Manual or further discussion of the BMU instructions.
F3 ALU Instructions
Cacheable (one-cycle)
aD = aS + aT
aD = aS – aT
aD = aS & aT
aD = aS | aT
aD = aS ^ aT
aS – aT
aS & aT
aD = aS + p
aD = aS – p
aD = aS & p
aD = aS | p
aD = aS ^ p
aS – p
aS & p
Not Cacheable (two-cycle)
aD = aSh + IM16
aD = aSh – IM16
aD = aSh & IM16
aD = aSh | IM16
aD = aSh ^ IM16
aSh – IM16
aSh & IM16
aD = aSl + IM16
aD = aSl – IM16
aD = aSl & IM16
aD = aSl | IM16
aD = aSl ^ IM16
aSl – IM16
aSl & IM16
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