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參數(shù)資料
| 型號(hào)： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 97/127頁(yè) |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 97 of 127
The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
Cycle 1A
: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index
of the comparand register pair that will be written in the data array in the 136-bit-configured table. For a Learn in a 68-bit-con-
figured table, the even-numbered comparand specified by this index will be written. CMD[8:7] carries the bits that will be driven
on SADR[21:20] in the SRAM Write cycle.
Cycle 1B
: The host ASIC continues to drive the CMDV to 1, the CMD[1:0] to 11, and the CMD[5:2] with the comparand pair
index. CMD[6] must be set to 0 if the Learn is being performed on a 68-bit-configured table, and to 1 if the Learn is being
performed on a 136-bit-configured table.
Cycle 2
: The host ASIC drives the CMDV to 0.
At the end of cycle 2, a new instruction can begin. The latency of the SRAM Write is the same as the Search to the SRAM Read
cycle. It is measured from the second cycle of the Learn instruction.
11.0
Depth-Cascading
The Search engine application can depth-cascade the devices to various table sizes of different widths (68 bits, 136 bits, or 272
bits). The devices perform all the necessary arbitration to decide which device will drive the SRAM bus. The latency of the
searches increases as the table size increases; the Search rate remains constant.
Table 10-34. The Latency of SRAM Write Cycle from Second Cycle of Learn Instruction
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Latency in CLK Cycles
4
5
6
cycle
1
Learn1
Learn2
CLK2X
CMDV
CMD[1:0]
DQ
SADR[21:0]
CE_L
CMD[8:2]
X
WE_L
OE_L
X
X
X
X
X
TLSZ = 01, LRAM = 1, LDEV = 1.
Figure 10-75. Timing Diagram of Learn on Device Number 7 (TLSZ = 01)
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
X
X
1A1B
Comp1
Comp2
X
PHS_L
1
1
0
z
z
z
z
z
z
z
z
z
0
0
SSV
SSF
1
1
1
0
z
1
1
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