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| 型號： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 45/127頁 |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 45 of 127
The following is the sequence of operation for a single 68-bit Search command (also refer to the “Command and Command
Parameters,” Subsection 10.2 on page 18).
Cycle A
: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:7] signals must be driven with
the same bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data to
be compared. The CMD[2] signal must be driven to a logic 0.
Cycle B
: The host ASIC continues to drive the CMDV HIGH and applies Search command (10) on CMD[1:0]. CMD[5:2] must
be driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A
and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and the hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be
compared.
Note
. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B and the even
and odd pair of global mask registers selected for the compare must be programmed with the same value.
cycle
1
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
CMD[8:2]
Search2
Search4
WE_L
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1.
Note: |(BHI[2:0)] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
PHS_L
SADR[21:0]
SSF
SSV
ALE_L
Search1
(Hit on
some
device
above.)
Search2
(Hit on
some
device
above.)
Search4
(Global
miss; this device
default driver.)
D1
D2
D3
D4
01
01
01
01
Search1
Search3
A B A B A B A B
z
0
0
LHO[1:0]
0
I(BHI[2:0])
0
Search3
(Hit on
some
device
above.)
|(LHI[6:0])
0
BHO[2:0]
0
z
0
0
0
z
1
z
1
0
0
z
z
0
1
Figure 10-25. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in Depth-Cascaded Table)
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