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| 型號(hào)： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 15/127頁(yè) |
| 文件大?。?/td> | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 15 of 127
7.5
Table 7-4
describes the information register fields.
Information Register
TLSZ
[3:2]
01
Table Size
. The host ASIC must program this field to configure the chips into a table of a certain
size. This field affects the pipeline latency of the Search and Learn operations as well as the
Read and Write accesses to the SRAM (SADR[21:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF,
and ACK). Once programmed, the Search latency stays constant.
Latency in number of CLK cycles
00: One device
4
01: Up to eight devices
5
10: Up to 31 devices
6
11: Reserved.
Latency of Hit Signals
.
This field further adds latency to the SSF and SSV signals during
Search, and ACK signal during SRAM Read access by the following number of CLK cycles.
000: 0 100: 4
001: 1 101: 5
010: 2 110: 6
011: 3 111: 7
Last Device in the Cascade
. When set, this is the last device in the depth-cascaded table and
is the default driver for the SSF and SSV signals. In the event of a Search failure, the device
with this bit set drives the hit signals as follows: SSF = 0, SSV = 1.
During nonSearch cycles, the device with this bit set drives the signals as follows: SSF = 0,
SSV = 0.
Last Device on the SRAM Bus
. When set, this device is the last device on the SRAM bus in
the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L
signals. In cycles where no CYNSE70064A device in a depth-cascaded table drives these
signals, this devices drives the signals as follows: SADR = 22’h3FFFFF, CE_L = 1, WE_L = 1,
and ALE_L = 1. OE_L is always driven by the device for which this bit is set.
Database Configuration
. The device is divided internally into four partitions of 8K × 68, each
of which can be configured as 8K × 68, 4K × 136, or 2K × 272, as follows.
00: 8K × 68
01: 4K × 136
10: 2K × 272
11: Reserved
Bits [10:9] apply to configuring the first partition in the address space.
Bits [12:11] apply to configuring the second partition in the address space.
Bits [14:13] apply to configuring the third partition in the address space.
Bits [16:15] apply to configuring the fourth partition in the address space.
Reserved
.
HLAT
[6:4]
000
LDEV
[7]
0
LRAM
[8]
0
CFG
[16:9]
00000000
[67:17]
0
Table 7-4. Information Register Description
Field
Revision
Range
[3:0]
Initial Value
000
[4]
Description
Revision Number
. This is the current device revision number. Numbers
start at one and increment by one for each revision of the device.
This is the CYNSE70064A implementation number.
Reserved
.
This is the device identification number.
Reserved
.
These are the three MSBs of the device identification number.
1101_1100_0111_1111
Manufacturer ID
. This field is the same as the manufacturer identification
number and continuation bits in the TAP controller.
Reserved
.
Implementation
Reserved
Device ID
Device ID
Device ID
MFID
[6:4]
[7]
[11:8]
[12]
[15:13]
[31:16]
000 or 001
0
0001 or 0010
0 or 1
000
Reserved
[67:32]
Note:
4.
This field may change in future versions.
Table 7-3. Command Register Description
(continued)
Field
Range
Initial Value
Description
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| CYP15G0402DX-BGC | Quad HOTLinkII SERDES |
| CYP15G0402DX | Quad HOTLinkII SERDES |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CYNSE70128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Network Processing |
| CYNSE70128-83BGC | 制造商:Cypress Semiconductor 功能描述:NETWORK SEARCH ENGINE 388BGA - Trays |
| CYNSE70128-83BGI | 制造商:Cypress Semiconductor 功能描述:NETWORK SEARCH ENGINE 388BGA - Trays |
| CYNSE70129HV-200BGC | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70131-250BBC | 制造商:Cypress Semiconductor 功能描述: |
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