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參數(shù)資料
| 型號(hào)： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 108/127頁(yè) |
| 文件大?。?/td> | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 108 of 127
12.6
SRAM Write enables Write access to the off-chip SRAM that contains associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the TLSZ value parameter programmed in the device configuration register. The following explains the SRAM Write operation
accomplished through a table of only one device with the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and
LDEV = 1.
Figure 12-8
shows the timing diagram. For the following description the selected device refers to the only device in
the table as it is the only device that will be accessed.
Cycle 1A
: The host ASIC applies the Write instruction on the CMD[1:0], using CMDV = 1. The DQ bus supplies the address
with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. The host ASIC also supplies SADR[21:20] on CMD[8:7] in this cycle.
Note
. CMD[2] must be set to 0 for SRAM
Write as burst Writes into the SRAM are not supported.
Cycle 1B
: The host ASIC continues to apply the Write instruction on the CMD[1:0], using CMDV = 1. The DQ bus supplies
the address with DQ[20:19] set to 10 to select the SRAM address. Note that CMD[2] must be set to 0 for SRAM Write as burst
Writes into the SRAM are not supported.
Cycle 2
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
Cycle 3
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, however the Write cycle appears at the
SRAM bus with the same latency as the latency of Search instruction as measured from the second cycle of the Write command.
SRAM Write with a Table of One Device
cycle
1
CLK2X
CE_L
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
PHS_L
SADR[21:0]
SSF
SSV
1
0
0
CMDV
CMD[1:0]
CMD[8:2]
00
Read
A B
Address
DQ
z
1
WE_L
OE_L
0
ALE_L
1
z
z
1
z
ACK
z
1
1
TLSZ = 10, HLAT = 010, LRAM = 1, LDEV = 1
Figure 12-7. SRAM Read Through Device Number 0 in Bank of 31 Devices
(Device Number 30 Timing)
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