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| 型號(hào)： | CYNSE70064A-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 22/127頁(yè) |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A-83BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 22 of 127
Table 10-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write)
Figure 10-4
shows the timing diagram of a burst Write operation of the data or mask array.
The burst Write operation lasts for (n + 2) CLK cycles. n signifies the number of accesses in the burst as specified in the BLEN
field of the WBURREG register. The following is the block Write operation sequence. This operation assumes that the host ASIC
has programmed the WBURREG with the starting address (ADR) and the length of transfer (BLEN) before initiating a burst Write
command.
Cycle 1A
: The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the address supplied
on the DQ bus, as shown in
Table 10-9
. The host ASIC also supplies the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3].
Cycle 1B
: The host ASIC continues to apply the Write instruction on the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the
address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3]. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. It selects all the
devices when DQ[25:21] = 11111.
DQ
[67:30]
Reserved 0: Direct
DQ[29]
DQ[28:26]
SSR (appli-
cable if DQ[29]
is indirect)
DQ
[25:21]
ID
DQ[20:19]
00: Data Array Reserved If DQ[29] is 0, this field carries the address of the data
array location.
If DQ[29] is 1, the SSR specified on DQ[28:26] is used
to generate the address of data array location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
[6]
01: Mask Array Reserved If DQ[29] is 0, this field carries the address of the mask
array location.
If DQ[29] is 1, the SSR specified on DQ[28:26] is used
to generate the address of the mask array location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
[6]
10: External
SRAM
SRAM location.
If DQ[29] is 1, the SSR specified on DQ[28:26] is used
to generate the address of SRAM location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
[6]
DQ
[18:15]
DQ[14:0]
1: Indirect
Reserved 0: Direct
1: Indirect
SSR (appli-
cable if DQ[29]
is indirect)
ID
Reserved 0: Direct
1: Indirect
SSR (appli-
cable if DQ[29]
is indirect)
ID
Reserved If DQ[29] is 0, this field carries the address of the
Table 10-8. Write Address Format for Internal Registers
DQ[67:26]
DQ[25:21]
Reserved
DQ[20:19]
11: Register
DQ[18:6]
Reserved
DQ[5:0]
ID
Register address
1
Data0
Data1 Data2
X
Data3
Write
Address
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
CMD[1:0]
DQ
CLK2X
EOT
CMD[8:2]
A
B
PHS_L
CMDV
Figure 10-4. Burst Write of the Data and Mask Arrays (BLEN = 4)
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